Stacked DRAM memory chip for a dual inline memory module (DIMM)

• US 7,200,021 B2
• Filed: 12/10/2004
• Issued: 04/03/2007
• Est. Priority Date: 12/10/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Raghuram, Siva
• Primary Examiner(s): Hoang; Huan
• Assistant Examiner(s): Graham; Kretelia
• Application Number:
  US11/010,942
• Publication Number:
  US 20060126369A1
• Time in Patent Office: 844 Days
• Field of Search: 365/51, 257/686
• US Class Current: 365/51
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A stacked DRAM memory chip for a Dual In Line Memory Module (DIMM) is disclosed. According to one aspect, the DRAM memory chip comprises at least four stacked DRAM memory dies. Further, the memory dies are each selectable by a corresponding internal memory rank signal. Each memory die comprises an array of memory cells. A common internal address bus is provided for addressing the memory cells and is connected to all stacked DRAM memory dies. Internal data buses are provided for writing data into the memory cells and reading data out of the memory cells of the DRAM memory dies. An integrated redriving unit comprises buffers for all internal address lines provided for driving external address signals applied to address pads of the DRAM memory chip. A multiplexer/demultiplexer switches the internal data lines of the selected DRAM memory die. A memory rank decoder selects a corresponding memory die.

Claims

1. A stacked DRAM Memory Chip for a Dual In Line Memory Module comprising:

(a) a predetermined number of at least four stacked DRAM memory dies;

(b) wherein the stacked DRAM memory dies are each selectable by a corresponding internal memory rank signal;

(c) wherein each DRAM memory die comprises an array of memory cells;

(d) wherein a common internal address bus consisting of internal address lines is provided for addressing the memory cells and is connected to all stacked DRAM memory dies;

(e) wherein internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies;

wherein

(f) an integrated redriving unit is provided which comprises;

(f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said stacked DRAM memory chip;

(f2) a multiplexer/demultiplexer which switches the internal data lines of the selected DRAM memory die to data pads of said stacked DRAM memory chip; and

(f3) a memory rank decoder for generating the internal memory rank signal to select a corresponding stacked DRAM memory die in response to external select signals applied to control pads of the stacked DRAM memory chip via an external selection signal bus, wherein a bus width S of the external selection signal bus depends on a number N of DRAM memory chips on the Dual In Line Memory Module and the predetermined number M of stacked DRAM memory dies within the DRAM memory chip as follows;

2^S=N+M.

2. The stacked DRAM Memory Chip according to claim 1, wherein the memory rank decoder controls the multiplexer/demultiplexer.

3. The stacked DRAM memory chip according to claim 1, wherein the multiplexer/demultiplexer is switched between a multiplexing mode and a demultiplexing mode in response to a Write Enable control signal.

4. The stacked DRAM Memory Chip according to claim 1, wherein the multiplexer/demultiplexer comprises buffers for driving data signals transmitted via the switched internal data lines.

5. The stacked DRAM Memory Chip according to claim 1, wherein all stacked DRAM memory dies are clocked by a common internal clock signal.

6. The stacked DRAM Memory Chip according to claim 5, wherein the integrated redriving unit further comprises a buffer for driving an external clock signal applied to a clock pad of the stacked DRAM memory chip to generate said common internal clock signal.

7. The stacked DRAM Memory Chip according to claim 1, wherein the stacked DRAM memory dies and the integrated redriving unit are integrated in the stacked DRAM memory chip.

8. The stacked DRAM Memory Chip according to claim 1, wherein the integrated redriving unit is powered via power supply pads of said stacked DRAM memory chip.

9. A Dual In Line Memory Module comprising a plurality of stacked DRAM memory chips, wherein each stacked DRAM memory chip comprises:

(a) a predetermined number of at least four stacked DRAM memory dies;

(b) wherein the stacked DRAM memory dies are each selectable by a corresponding internal memory rank signal;

(c) wherein each DRAM memory die comprises an array of memory cells;

(d) wherein a common internal address bus consisting of internal address lines is provided for addressing the memory cells and is connected to all stacked DRAM memory dies;

(e) wherein internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies;

(f) wherein an integrated redriving unit is provided which comprises;

(f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said stacked DRAM memory chip;

(f2) a multiplexer/demultiplexer which switches the internal data lines of the selected stacked DRAM memory die to data pads of said stacked DRAM memory chip; and

(f3) a memory rank decoder for generating the internal memory rank signal to select a corresponding stacked DRAM memory die in response to external select signals applied to control pads of the stacked DRAM memory chip via an external selection signal bus, wherein a bus width S of the external selection signal bus depends on a number N of DRAM memory chips on the Dual In Line Memory Module and the predetermined number M of stacked DRAM memory dies within said DRAM memory chip as follows;

2^S=N+M.

10. The Dual In Line Memory Module according to claim 9, wherein the Dual In Line Memory Module further comprises a command and address buffer chip for buffering command and address signals received from a main printed circuit board.

11. The Dual In Line Memory Module according to claim 10, wherein the command and address buffer is connected via a command and address bus and the external rank selection signal bus to all stacked DRAM memory chips mounted on a printed circuit board of said Dual In Line Memory Module.