System and method for optically interconnecting memory devices
First Claim
1. A memory device, comprising:
- a semiconductor substrate;
an address converter fabricated in the substrate, the address converter being operable to receive and convert optical address signals into corresponding electrical address signals;
an address decoder fabricated in the semiconductor substrate, the address decoder being coupled to the address converter to receive the electrical address signals from the address converter;
a data converter fabricated in the substrate, the data converter being operable to receive and convert optical write data signals into corresponding electrical write data signals and to receive and convert electrical read data signals into corresponding optical read data signals;
a read/write circuit fabricated in the semiconductor substrate, the read/write circuit being coupled to the data converter to receive the electrical read data signals from the data converter and to couple the electrical write data signals to the data converter;
a control signal converter fabricated in the substrate, the control signal converter being operable to receive and convert optical control signals into corresponding electrical control signals;
a control logic unit fabricated in the semiconductor substrate, the control logic unit being coupled to the control signal converter; and
a memory-cell array fabricated in the semiconductor substrate, the memory-cell array being coupled to the address decoder, control logic unit, and read/write circuit.
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Accused Products
Abstract
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into corresponding electrical address signals applied to the address decoder and control signals applied to the control logic. A read/write circuit on the substrate is coupled to a data converter formed in the substrate. The data converter is operable to receive and convert optical write data signals into corresponding electrical data signals to be applied to the read/write circuit and to receive and convert electrical read data signals into corresponding optical read data signals.
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Citations
39 Claims
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1. A memory device, comprising:
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a semiconductor substrate; an address converter fabricated in the substrate, the address converter being operable to receive and convert optical address signals into corresponding electrical address signals; an address decoder fabricated in the semiconductor substrate, the address decoder being coupled to the address converter to receive the electrical address signals from the address converter; a data converter fabricated in the substrate, the data converter being operable to receive and convert optical write data signals into corresponding electrical write data signals and to receive and convert electrical read data signals into corresponding optical read data signals; a read/write circuit fabricated in the semiconductor substrate, the read/write circuit being coupled to the data converter to receive the electrical read data signals from the data converter and to couple the electrical write data signals to the data converter; a control signal converter fabricated in the substrate, the control signal converter being operable to receive and convert optical control signals into corresponding electrical control signals; a control logic unit fabricated in the semiconductor substrate, the control logic unit being coupled to the control signal converter; and a memory-cell array fabricated in the semiconductor substrate, the memory-cell array being coupled to the address decoder, control logic unit, and read/write circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory module, comprising:
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an insulative substrate; a plurality of memory devices mounted on the substrate, each memory device comprising; a semiconductor substrate; a plurality of electrical input and output terminals fabricated in the semiconductor substrate including electrical data terminals operable to output read data signals and input write data signals, and electrical address and control terminals operable to input address and control signals; a plurality of optical receivers fabricated in the semiconductor substrate coupled to corresponding data, control and address terminals, the receivers being operable to receive optical signals and translate the optical signals into corresponding electrical signals; a plurality of optical transmitters fabricated in the semiconductor substrate coupled to corresponding data terminals, the optical transmitters being operable to receive read data signals and translate the read data signals into corresponding optical read data signals; and a plurality of optical paths coupled to the optical receivers and transmitters. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of communicating control and address signals to and/or from a memory device, comprising:
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coupling optical signals corresponding to control and address signals to the memory device; receiving the optical control and address signals in the memory device; developing electrical control and address signals on the memory device corresponding to the optical control and address signals; and accessing a memory location within the memory device in accordance with the control and address signals. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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30. A method of communicating control and address signals to a memory device, comprising:
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coupling optical signals corresponding to control and address signals from a memory hub to the memory device; receiving the optical control and address signals in the memory device; developing electrical control and address signals in the memory device corresponding to the optical control and address signals; and accessing a memory location within the memory device in accordance with the control and address signals. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification