Semiconductor memory device
First Claim
1. A semiconductor memory device comprising a memory cell array in which a plurality of static type memory cells comprised of a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs accessing to the latch circuit are arranged, the semiconductor memory device comprising:
- a switch for controlling a source line connected to a source electrode of a said driver MOSFET and a ground potential line so that the source line and the around potential line are connected in an operational state of said memory cells and not connected in a standby state of said memory cells;
a source potential control circuit connected between said source line and said ground potential;
wherein, in the standby state of said memory cells, a source potential is set to an intermediate potential between the ground potential and the supply potential by said source potential control circuit; and
wherein said source potential control circuit includes at least first and second elements connected in parallel with each other, said first element having a resistance less than a resistance of said second element and predetermined according to a value of Vth of said driver MOSFETs and said transfer MOSFETs.
3 Assignments
0 Petitions
Accused Products
Abstract
When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
-
Citations
17 Claims
-
1. A semiconductor memory device comprising a memory cell array in which a plurality of static type memory cells comprised of a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs accessing to the latch circuit are arranged, the semiconductor memory device comprising:
-
a switch for controlling a source line connected to a source electrode of a said driver MOSFET and a ground potential line so that the source line and the around potential line are connected in an operational state of said memory cells and not connected in a standby state of said memory cells; a source potential control circuit connected between said source line and said ground potential; wherein, in the standby state of said memory cells, a source potential is set to an intermediate potential between the ground potential and the supply potential by said source potential control circuit; and wherein said source potential control circuit includes at least first and second elements connected in parallel with each other, said first element having a resistance less than a resistance of said second element and predetermined according to a value of Vth of said driver MOSFETs and said transfer MOSFETs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A semiconductor memory device comprising a memory circuit in which static type memory cells are provided at an intersection point of a word line and a bit line and arranged in an array-like manner, wherein
said memory cells are comprised of a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs accessing to the latch circuit; -
the semiconductor memory device has a source potential control circuit for controlling a potential of a source line connected to a source electrode of said driver MOSFET; and a negative voltage is applied to the word line connected to the memory cells that are not selected in the operational state of said memory circuit and the word line is set to a ground potential in the standby state of said memory circuit; and wherein said source potential control circuit includes at least first and second elements connected in parallel to each other, said first element having a resistance less than a resistance of said second element and predetermined according to a value of Vth of said driver MOSFETs and said transfer MOSFETs. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. A semiconductor memory device comprising a memory array in which static type memory cells comprised of a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs accessing to the latch circuit are arranged in an array-like manner, wherein the semiconductor memory device has a source potential control circuit for controlling a potential of a source line connected to a source electrode of said driver MOSFET;
-
wherein a MOSFET disposed in a first area in which said memory cells are arranged in a direction perpendicular to the bit line at one end of said memory array is provided, a portion of a gate layer of the MOSFET disposed in said first area is connected to a ground potential and the other portion of said gate layer is connected to a signal line for controlling an operational potential of the memory cells; and wherein said source potential control circuit includes at least first and second elements connected in parallel to each other, said first element having a resistance less than a resistance of said second element and predetermined according to a value of Vth of said driver MOSFETs and said transfer MOSFETs. - View Dependent Claims (16, 17)
-
Specification