Semiconductor memory device

• US 7,200,030 B2
• Filed: 12/12/2003
• Issued: 04/03/2007
• Est. Priority Date: 12/24/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yanagisawa, Kazumasa, Yamaoka, Masanao, Osada, Kenichi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/733,270
• Publication Number:
  US 20040125681A1
• Time in Patent Office: 1,208 Days
• Field of Search: 365/154, 365/156, 365/226, 365/227, 327/143
• US Class Current: 365/154
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Claims

1. A semiconductor memory device comprising a memory cell array in which a plurality of static type memory cells comprised of a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs accessing to the latch circuit are arranged, the semiconductor memory device comprising:

a switch for controlling a source line connected to a source electrode of a said driver MOSFET and a ground potential line so that the source line and the around potential line are connected in an operational state of said memory cells and not connected in a standby state of said memory cells;

a source potential control circuit connected between said source line and said ground potential;

wherein, in the standby state of said memory cells, a source potential is set to an intermediate potential between the ground potential and the supply potential by said source potential control circuit; and

wherein said source potential control circuit includes at least first and second elements connected in parallel with each other, said first element having a resistance less than a resistance of said second element and predetermined according to a value of Vth of said driver MOSFETs and said transfer MOSFETs.

2. A semiconductor memory device according to claim 1, wherein said source potential control circuit is comprised of an n-channel MOSFET in which a drain electrode and a gate electrode are connected to said source line and the source electrode is connected to said ground potential line.

3. A semiconductor memory device according to claim 1, wherein said source potential control circuit is comprised of:

an n-channel MOSFET in which a drain electrode and a gate electrode are connected to said source line and the source electrode is connected to said ground potential line; and

a resistance that connects between said source line and said ground potential line.

4. A semiconductor memory device according to claim 3, wherein said resistance is comprised of an n-channel MOSFET in which a drain electrode is connected to said source line, a source electrode is connected to said ground potential line, and a gate electrode is connected to said supply potential line.

5. A semiconductor memory device according to claim 1, wherein said switch is a switch MOS that is comprised of an n-channel MOSFET in which a drain electrode, a source electrode and a gate electrode are connected to said source line, said ground potential line, and a control signal line for controlling said switch, respectively.

6. A semiconductor memory device according to claim 5, wherein said switch MOS is disposed between said memory cell array and a sense amplifier that operates when data is read out.

7. A semiconductor memory device according to claim 1, comprising:

an access circuit for accessing said memory cells; and

a switch that is connected between an operational potential point and a supply potential line of said access circuit.

8. A semiconductor memory device according to claim 7, wherein said access circuit comprises:

a word driver for driving a word line;

a first switch disposed between a high operational potential point of said word driver and the supply potential line; and

a second switch disposed between a low operational potential point of circuits accessing said memory cells except the word driver and the supply potential line.

9. A semiconductor memory device comprising a memory circuit in which static type memory cells are provided at an intersection point of a word line and a bit line and arranged in an array-like manner, wherein

said memory cells are comprised of a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs accessing to the latch circuit;

the semiconductor memory device has a source potential control circuit for controlling a potential of a source line connected to a source electrode of said driver MOSFET; and

a negative voltage is applied to the word line connected to the memory cells that are not selected in the operational state of said memory circuit and the word line is set to a ground potential in the standby state of said memory circuit; and

wherein said source potential control circuit includes at least first and second elements connected in parallel to each other, said first element having a resistance less than a resistance of said second element and predetermined according to a value of Vth of said driver MOSFETs and said transfer MOSFETs.

10. A semiconductor memory device according to claim 9, wherein, when data is read out from said memory circuit, said source potential is set to the ground potential and, when the data is written to said memory circuit or in the standby state, said source line potential is set to an intermediate potential between the ground potential and a supply potential by said source potential control circuit.

11. A semiconductor memory device according to claim 9, wherein a drain electrode of said transfer MOSFET is connected to the bit line and, when said source line is set to an intermediate potential between the ground potential and the supply potential, the potential of said bit line is set to the supply potential.

12. A semiconductor memory device according to claim 9, wherein a threshold voltage of said driver MOSFET is higher than a threshold voltage of said transfer MOSFET.

13. A semiconductor memory device according to claim 9, wherein an absolute value of the threshold voltages of said transfer MOSFET and said driver MOSFET is lower than an absolute value of a threshold voltage of said load MOSFET.

14. A semiconductor memory device according to claim 9, wherein a logic circuit including a first MOSFET having a first threshold voltage and a second MOSFET having a second threshold voltage higher than said first threshold voltage is packaged together on a substrate on which said memory circuit is disposed, and wherein said first MOSFET is used as said transfer MOSFET and said second MOSFET is used as said driver MOSFET.

15. A semiconductor memory device comprising a memory array in which static type memory cells comprised of a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs accessing to the latch circuit are arranged in an array-like manner, wherein the semiconductor memory device has a source potential control circuit for controlling a potential of a source line connected to a source electrode of said driver MOSFET;

wherein a MOSFET disposed in a first area in which said memory cells are arranged in a direction perpendicular to the bit line at one end of said memory array is provided, a portion of a gate layer of the MOSFET disposed in said first area is connected to a ground potential and the other portion of said gate layer is connected to a signal line for controlling an operational potential of the memory cells; and

wherein said source potential control circuit includes at least first and second elements connected in parallel to each other, said first element having a resistance less than a resistance of said second element and predetermined according to a value of Vth of said driver MOSFETs and said transfer MOSFETs.

16. A semiconductor memory device according to claim 15, wherein, in a layout pattern of said memory cells, said pair of driver MOSFETs, said pair of transfer MOSFETs and said load device are arranged symmetrically with respect to a predetermined point in the pattern of said memory cells.

17. A semiconductor memory device according to claim 15, wherein a portion of said MOSFET formed in said first area is used for as a switch.