Memory module with termination component

• US 7,200,055 B2
• Filed: 09/01/2005
• Issued: 04/03/2007
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): Dinh; Son
• Assistant Examiner(s): Luu; Pho M.
• Application Number:
  US11/219,381
• Publication Number:
  US 20060007761A1
• Time in Patent Office: 579 Days
• Field of Search: 365/194, 365/189.01, 365/189.04, 365/191, 365/230.01, 365/233
• US Class Current: 365/194
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory module having a termination component. The memory module includes first and second memory devices, a termination component and three sets of signal lines. A first set of signal lines is coupled to the first memory device and dedicated to data transfers involving the first memory device. A second signal lines is coupled to the second memory device and dedicated to data transfers involving the second memory device. A third set of signal lines is coupled to the first and second memory devices and the termination component such that a signal propagating on the third set of signal lines propagates past the first memory device before reaching the second memory device, and propagates past the second memory device before reaching the termination component.

Claims

1. A memory module comprising:

a first memory device;

a first plurality of signal lines coupled to the first memory device, the first plurality of signal lines being dedicated to data transfers involving the first memory device;

a second memory device;

a second plurality of signal lines coupled to the second memory device, the second plurality of signal lines dedicated to data transfers involving the second memory device;

a first termination component; and

a third plurality of signal lines coupled to the first memory device, the second memory device, and the first termination component such that a signal propagating on the third plurality of signal lines propagates past the first memory device before reaching the second memory device and propagates past the second memory device before reaching the first termination component, the third plurality of signal lines including a signal line to convey, at different times, row address information and column address information to the first and second memory devices.

2. The memory module of claim 1, further comprising a signal line to convey a clock signal that indicates a first time at which the signal propagating on the third plurality of signal lines is to be sampled by the first memory device, wherein the clock signal also indicates a second time at which the signal propagating on the third plurality of signal is to be sampled by the second memory device.

3. The memory module of claim 1, further comprising:

a first signal line coupled to the first memory device, the first signal line to convey a first timing signal that is associated with the data transfers involving the first memory device; and

a second signal line coupled to the second memory device, the second signal line to convey a second timing signal that is associated with the data transfers involving the second memory device.

4. The memory module of claim 1, further comprising:

a second termination component coupled to the first plurality of signal lines, wherein the second termination component is disposed on the first memory device; and

a third termination component coupled to the second plurality of signal lines, wherein the third termination component is disposed on the second memory device.

5. A memory module comprising:

a first memory device;

a second memory device;

a termination component;

a control signal path coupled to the first memory device, the second memory device, and the termination component, wherein the control signal path includes at least a first portion, a second portion and a third portion, wherein, before reaching the first memory device, signals propagating on the control signal path propagate on a first portion of the control signal path but not on the second or third portions of the control signal path, wherein, before reaching the second memory device, the signals propagate on the first and second portions of the control signal path but not the third portion of the control signal path, and wherein the signals propagate on the first, second and third portions of the control signal path before reaching the termination component, the control signal path including a signal line to convey, at different times, row address information and column address information to the first and second memory devices;

a first data signal path coupled to the first memory device but not the second memory device; and

a second data signal path coupled to the second memory device but not the first memory device.

6. A memory system comprising:

a first memory device;

a first plurality of signal lines coupled to the first memory device, the first plurality of signal lines to exchange data with the first memory device;

a second memory device;

a second plurality of signal lines coupled to the second memory device, the second plurality of signal lines to exchange data with the second memory device;

a termination component;

a third plurality of signal lines coupled to the first memory device, the second memory device, and the termination component such that signals propagating on the third plurality of signal lines propagates past the first memory device and the second memory device before reaching the termination component, the third plurality of signal lines including a signal line to convey, at different times, row address information and column address information to the first and second memory devices; and

a clock line coupled to the first memory device and the second memory device, wherein the clock line is routed alongside the third plurality of signal lines and carries a clock signal, wherein the first memory device samples the signals propagating on the third plurality of signal lines using the clock signal and the second memory device samples the signals propagating on the third plurality of signal lines using the clock signal.

7. The memory system of claim 6, wherein the signals propagating on the third plurality of signal lines are representative of control information and address information.

8. The memory system of claim 6, further comprising:

a first signal line coupled to the first memory device, the first signal line to convey a first timing signal that is associated the exchange of data with the first memory device; and

a second signal line coupled to the second memory device, the second signal line to convey a second timing signal that is associated with the exchange of data with the second memory device.

9. The memory system of claim 6, further comprising:

a second termination component coupled to the first plurality of signal lines, wherein the second termination component is disposed on the first memory device; and

a third termination component coupled to the second plurality of signal lines, wherein the third termination component is disposed on the second memory device.

10. The memory system of claim 6 further comprising:

a memory controller coupled to the first memory device and the second memory device, the memory controller including;

timing circuitry to delay transmission of a data transfer to the first memory device by a first time interval that is based, at least in part, on an amount of time required for the signals propagating on the third plurality of signal lines to propagate from the memory controller to the first memory device; and

timing circuitry to delay transmission of a data transfer to the second memory device by a second time interval that is based, at least in part, on an amount of time required for the signals propagating on the third plurality of signal lines to propagate from the memory controller to the second memory device.

11. A memory system comprising:

a controller device;

a first memory device;

a first plurality of signal lines coupled to the first memory device and the controller device, the first plurality of signal lines being dedicated to transferring first data between the controller device and the first memory device;

a second memory device;

a second plurality of signal lines coupled to the second memory device and the controller device, the second plurality of signal lines dedicated to transferring second data between the controller device and the second memory device;

a first termination component; and

a third plurality of signal lines coupled to the first memory device, the second memory device and the first termination component such that signals propagating on the third plurality of signal lines propagate past the first memory device before reaching the second memory device and propagate past the second memory device before reaching the first termination component, the third plurality of signal lines including a signal line to convey, at different times, row address information and column address information to the first and second memory devices.

12. The memory system of claim 11, further comprising:

a second termination component disposed on the first memory device, wherein the second termination component is coupled to the first plurality of signal lines; and

a third termination component disposed on the second memory device, wherein the third termination component is coupled to the second plurality of signal lines.

13. The memory system of claim 11, wherein the third plurality of signal lines includes signal lines to carry address signals to the first memory device and the second memory device.

14. The memory system of claim 13, wherein the third plurality of signal lines includes signal lines to carry control signals to the first memory device and the second memory device.

15. The memory system of claim 11, wherein the third plurality of signal lines includes signal lines to provide control information to the first memory device and the second memory device, and address information to the first memory device and the second memory device.

16. The memory system of claim 11, further comprising a signal line to convey a timing signal that indicates a first time at which the signals propagating on the third plurality of signal lines are to be sampled by the first memory device, wherein the timing signal also indicates a second time at which the signals propagating on the third plurality of signal lines is to be sampled by the second memory device.

17. The memory system of claim 16, wherein the timing signal is a strobe signal.

18. The memory system of claim 16, wherein the signal line extends alongside the third plurality of signal lines such that the timing signal propagates past each of the memory devices in the same order as the signals propagating on the third plurality of signal lines.

19. The memory system of claim 11, further comprising:

a first signal line that extends alongside the first plurality of signal lines, the first signal line to convey a first timing signal that indicates a time at which the first data is to be sampled by the first memory device; and

a second signal line that extends alongside the second plurality of signal lines, the second signal line to convey a second timing signal that indicates a time at which the second data is to be sampled by the second memory device.

20. The memory system of claim 19, wherein the memory controller comprises:

first timing circuitry to delay transmission of the first data onto the first plurality of signal lines by a time interval that is based, at least in part, on an amount of time required for the signals propagating on the third plurality of signal lines to propagate from the memory controller to the first memory device; and

first timing circuitry to delay transmission of the second data onto the second plurality of signal lines by a time interval that is based, at least in part, on an amount of time required for the signals propagating on the third plurality of signal lines to propagate from the memory controller to the second memory device.

21. The memory system of claim 19, wherein the first timing signal is a strobe signal, and the second timing signal is a strobe signal.

22. A memory module comprising:

a first memory device including a first termination component;

a first plurality of data lines coupled to the first termination component;

a second memory device including a second termination component;

a second plurality of data lines coupled to the second termination component;

a third termination component; and

a plurality of signal lines coupled to the first memory device, the second memory device, and the third termination component such that a signal propagating on the plurality of signal lines propagates past the first memory device and the second memory device before reaching the third termination component, the plurality of signal lines including a signal line to convey, at different times, row address information and column address information to the first and second memory devices;

a clock line coupled to the first memory device and the second memory device, wherein the clock line is routed alongside the plurality of signal lines and carries a clock signal, wherein the first memory device samples the signal propagating on the plurality of signal lines using the clock signal, and wherein the second memory device samples the signal propagating on the plurality of signal lines using the clock signal.

23. A memory system comprising:

a first memory device;

a first plurality of signal lines coupled to the first memory device, the first plurality of signal lines to carry data in data transfers involving the first memory device;

a first termination component disposed on the first memory device and coupled to the first plurality of signal lines;

a second memory device;

a second plurality of signal lines coupled to the second memory device, the second plurality of signal lines to carry data in data transfers involving the second memory device;

a second termination component disposed on the second memory device and coupled to the second plurality of signal lines;

a third termination component; and

a third plurality of signal lines coupled to the first memory device, the second memory device, and the third termination component such that a signal propagating on the third plurality of signal lines propagates past the first memory device and the second memory device before reaching the third termination component, the third plurality of signal lines including a signal line to convey, at different times, row address information and column address information to the first and second memory devices;

a signal line to convey a clock signal that indicates a first time at which the signal propagating on the third plurality of signal lines is to be sampled by the first memory device, wherein the clock signal also indicates a second time at which the signal propagating on the third plurality of signal lines is to be sampled by the second memory device;

a first signal line coupled to the first memory device, the first signal line to convey a first strobe signal that is associated with the data transfers involving the first memory device; and

a second signal line coupled to the second memory device, the second signal line to convey a second strobe signal that is associated with the data transfers involving the second memory device.

24. A memory system comprising:

a first memory device;

a first plurality of signal lines to provide first data to the first memory device;

a first termination component disposed on the first memory device and coupled to the first plurality of signal lines;

a first signal line to convey a first timing signal that indicates a time at which the first data is to be sampled by the first memory device;

a second memory device;

a second plurality of signal lines to provide second data to the second memory device;

a second termination component disposed on the second memory device and coupled to the second plurality of signal lines;

a second signal line to convey a second timing signal that indicates a time at which the second data is to be sampled by the second memory device;

a third termination component; and

a third plurality of signal lines coupled to the first memory device, the second memory device, and the third termination component such that signals propagating on the third plurality of signal lines propagate past the first memory device and the second memory device before reaching the third termination component, the third plurality of signal lines including a signal line to convey, at different times, row address information and column address information to the first and second memory devices; and

a memory controller to provide the first data to the first memory device and the second data to the second memory device, the memory controller including;

first timing circuitry to delay transmission of the first data onto the first plurality of signal lines by a time interval that is based, at least in part, on an amount of time required for the signals, propagating on the third plurality of signal lines, to propagate from the memory controller to the first memory device; and

second timing circuitry to delay transmission of the second data onto the second plurality of signal lines by a time interval that is based, at least in part, on an amount of time required for the signals, propagating on the third plurality of signal lines, to propagate from the memory controller to the second memory device.