Modulator for digital amplifier

• US 7,200,187 B2
• Filed: 07/25/2002
• Issued: 04/03/2007
• Est. Priority Date: 07/26/2001
• Status: Expired due to Fees

• Current Assignee: O'Brien Audio, Inc.
• Original Assignee: O'Brien Audio, Inc.
• Inventors: O'Brien, Thomas J.
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): DSOUZA, JOSEPH FRANCIS A
• Application Number:
  US10/205,569
• Publication Number:
  US 20030031245A1
• Time in Patent Office: 1,713 Days
• Field of Search: 375/238, 375/316, 327/37, 327/172, 847/36, 370/213, 348/536, 341/143
• US Class Current: 375/316
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A digital modulator for driving a digital amplifier. The digital modulator has a subtractor which receives a digital input signal. A filter amplifier receives the output of the filter amplifier and is tuned to an idle frequency of the digital modulator. The digital modulator includes a delay element and a digital comparator. The digital comparator receives the output from the filter and applies it to the delay element. A feedback loop couples the output of the delay element to the subtractor.

Claims

1. A restricted modulation method comprising the steps of:

receiving an input signal that alternates between first and second states;

storing the input signal and providing the stored input signal as an output signal;

generating a first ramp signal responsive to the input signal and comparing the first ramp signal to a first threshold value and to a second threshold value, the first threshold value and the second threshold value associated with a pulse width of the input signal;

generating a second ramp signal responsive to the input signal and comparing the second ramp signal to a third threshold value associated with a pulse period of the input signal;

substituting the output signal for the input signal if the first ramp signal is less than the first threshold value or if the second ramp signal is less than the third threshold value; and

substituting an inverted output signal for the input signal if the first ramp signal is greater than the second threshold value.

2. A restricted modulator comprising:

a terminal which is configured to receive an input signal that alternates between first and second states;

a delay element which stores the input signal and provides the stored input signal as an output signal;

first arid second counters which count pulses of a clock signal to measure a) an amount of time for each state in the input signal to provide a pulse width value and b) an amount of time between successive changes from one of the first and second states to the other one of the first and second states to provide a pulse period value;

a multiplexer that substitutes the output signal for the input signal if the pulse width value is less than a first predetermined value or if the pulse period value is less than a second predetermined value and that substitutes an inverted output signal for the input signal if the pulse width value is greater than a third predetermined value.

3. A restricted modulator coupled to receive an input signal and to provide a modulated output signal, the restricted modulator comprising:

a first multiplexer having an output port, a first signal input port coupled to receive the input signal of the restricted modulator and a second signal input port coupled to receive the output signal, wherein the first multiplexer is responsive to a first control signal for selectively coupling the output port to one of the first and second input ports;

a second multiplexer, having an output port, a first input port coupled to receive an inverted version of the output signal of the modulator and a second input port coupled to the output port of the first multiplexer, wherein the second multiplexer is responsive to a second control signal for selectively coupling the output port of the second multiplexer to one of the first and second input ports of the second multiplexer;

a delay element, having a clock signal input port, a signal input port coupled to the output port of the second multiplexer and an output port which provides the output signal of the restricted modulator;

circuitry, coupled to the delay element for providing a difference pulse signal when a signal applied to the input port of the delay element differs from the output signal of the modulator;

a first counter, coupled to receive the clock signal and the difference pulse signal for generating a count value equal to a number of pulses of the clock signal between successive pulses of the difference pulse signal;

a second counter, coupled to receive the clock signal and the count value provided by the first counter, for loading the count value from the first counter responsive to a pulse of the difference signal and for incrementing its count value by one for each pulse of the clock signal until a next pulse of the difference signal;

reference circuitry coupled to receive the count value and the incremented count value for generating the first and second control signals, the first control signal being generated when the count value is less than a first reference value or when the incremented count value is less than a second reference value and the second control signal being generated when the count value is greater than a third predetermined value.

4. A digital modulator coupled to receive a digital input signal for driving a digital amplifier, the modulator comprising:

a subtractor having a first signal input port coupled to receive the digital input signal, a second signal input port coupled to receive a feedback signal, and an output port;

a digital filter amplifier having an input port coupled to the output port of the subtracter and an output port, the filter being tuned to an idle frequency of the digital modulator;

a delay element;

a digital comparator for receiving the filtered output of the filter and for applying the filtered output signal to the delay element, the delay element being coupled to the subtractor for providing a signal from the output of the delay element to the second input port of the subtracter; and

a restricted modulator comprising;

means for receiving the delayed output of the delay element as a restricted modulator input signal, the restricted modulator input signal alternating between first arid second states,

means for storing the restricted modulator input signal and providing the stored input signal as a restricted modulator output signal,

means for generating a first ramp signal responsive to the restricted modulator input signal and comparing the first ramp signal to a first threshold value end to a second threshold value, the first threshold value and the second threshold value with a ours width of the restricted modulator input signal,

means for generating a second ramp signal responsive to the restricted modulator input signal and comparing the second ramp signal to a third threshold value associated with a pulse period of the restricted modulator input signal,

means for substituting the restricted modulator output signal for the restricted modulator input signal if the first ramp signal is less than the first threshold value or if the second ramp signal is less than the third threshold value, and

means for substituting an inverted restricted modulator output signal for the restricted modulator input signal if the first ramp signal is greater than the second threshold value.