Method of implementing off-chip cache memory in dual-use SRAM memory for network processors
First Claim
1. A method, comprising:
- enabling a plurality of network processors to access a first shared memory store and a second shared memory store; and
employing a portion of the first shared memory store as a memory cache for the second shared memory store;
each network processor having a cache management component retrieving data from the memory cache, and a content addressable memory component performing content based searches of the first and second shared memory stores.
1 Assignment
0 Petitions
Accused Products
Abstract
A method, apparatus, and system for implementing off-chip cache memory in dual-use static random access memory (SRAM) memory for network processors. An off-chip SRAM memory store is partitioned into a resizable cache region and general-purpose use region (i.e., conventional SRAM use). The cache region is used to store cached data corresponding to portions of data contained in a second off-chip memory store, such as a dynamic RAM (DRAM) memory store or an alternative type of memory store, such as a Rambus DRAM (RDRAM) memory store. An on-chip cache management controller is integrated on the network processor. Various cache management schemes are disclosed, including hardware-based cache tag arrays, memory-based cache tag arrays, content-addressable memory (CAM)-based cache management, and memory address-to-cache line lookup schemes. Under one scheme, multiple network processors are enabled to access shared SRAM and shared DRAM, wherein a portion of the shared SRAM is used as a cache for the shared DRAM.
-
Citations
36 Claims
-
1. A method, comprising:
-
enabling a plurality of network processors to access a first shared memory store and a second shared memory store; and employing a portion of the first shared memory store as a memory cache for the second shared memory store; each network processor having a cache management component retrieving data from the memory cache, and a content addressable memory component performing content based searches of the first and second shared memory stores. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A computing apparatus comprising:
-
an internal interconnect; a first memory store, coupled with the internal interconnect via a first memory controller; a second memory store, coupled with the internal interconnect via a second memory controller; a cache management component coupled with the internal interconnect to effectuate a memory cache in a portion of the first memory store corresponding to data in the second memory store; and a content addressable memory component to perform content based searching of the first and second memory stores. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
-
-
22. A network processor, comprising:
-
an internal interconnect; a first memory controller coupled with the internal interconnect to access a first off-chip memory store; a second memory controller coupled with the internal interconnect to access a second off-chip memory store; a first portion of the first off-chip memory store configured as a memory cache for the second off-chip memory store; a cache management component coupled with the internal interconnect to retrieve data in the memory cache; a content addressable memory component to perform content based searching of the first and second off-chip memory stores; and a front side bus controller coupled with the internal interconnect to receive memory requests. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
-
-
31. A system, comprising:
-
a first memory store, with a first interface; a second memory store with a second interface; and a network processor comprising; an internal interconnect; a first memory controller coupled with the internal interconnect to access the first memory store; a second memory controller coupled with the internal interconnect to access the second memory store; a cache management component coupled with the internal interconnect to effectuate a memory cache in a portion of the first memory store corresponding to data in the second memory store; a content addressable memory component to perform content based searching of the first and second memory stores; and an interface controller coupled with the internal interconnect to receive memory requests via the second interface. - View Dependent Claims (32, 33, 34, 35, 36)
-
Specification