Operating-system-transparent distributed memory

• US 7,200,734 B2
• Filed: 07/31/2004
• Issued: 04/03/2007
• Est. Priority Date: 07/31/2004
• Status: Active Grant

• Current Assignee: Red Hat, Inc. (International Business Machines Corporation)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Hyser, Chris
• Primary Examiner(s): Elmore; Reba I.
• Application Number:
  US10/909,786
• Publication Number:
  US 20060041733A1
• Time in Patent Office: 976 Days
• Field of Search: 711/203, 711/206
• US Class Current: 711/203
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 2003/0697 device management, e.g. handlers, drivers, I/O schedulers
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46

Abstract

Various embodiments of the present invention provide distributed computing systems featuring an operating-system-transparent distributed memory that, among other things, facilitates shared-message-based inter-thread communication between intercommunicating threads executing concurrently on a single-processor computer system, concurrently and simultaneously on a multi-processor computer system, and concurrently and simultaneously on multiple, discrete computer systems. Certain embodiments of the present invention are implemented using a secure-platform architecture in which secure-platform code running on processors within a distributed computing system provide a virtual, or logical, computing platform on which operating systems and higher-level software can be layered. A distributed memory system is provided by the secure-platform layer, using an extension of the memory-management hardware, firmware, and software systems originally developed to support virtual memory in single-processor and multi-processor computer systems. In essence, logical processors, logical caches, logical memory, and logical mass-storage-device-implemented backing store are mapped onto the individual processors, caches, memories, and interconnected mass-storage systems of a number of discrete computer systems interconnected by high-speed networking.

Claims

1. A distributed computing system comprising:

a number of network-interconnected computer systems; and

a logical, distributed-computing layer, implemented from components of the network-interconnected computer systems, that provides

one or more logical processors;

one or more logical caches associated with each logical processor;

a logical, distributed memory; and

a logical backing store.

2. The distributed computing system of claim 1 wherein the logical, distributed-computing layer is a secure-platform layer.

3. The distributed computing system of claim 1 wherein to a logical processor is mapped one or more of:

a portion of a physical processor; and

a physical processor.

4. The distributed computing system of claim 1 wherein to a logical cache is mapped one or more of:

a physical cache;

a portion of a physical memory; and

a physical memory.

5. The distributed computing system of claim 1 wherein to the logical backing store is mapped one or more of:

a portion of a mass storage device;

a portion of a physical memory; and

a physical memory.

6. The distributed computing system of claim 1 wherein threads executing on different physical processors can communicate using shared-memory techniques employing the logical, distributed memory.

7. The distributed computing system of claim 1 wherein intercommunicating execution threads may be collocated on a logical processor to which one or more processors local to a particular computer system are mapped in order to avoid network-communications overhead.

8. The distributed computing system of claim 1 wherein a local computer system translates a virtual address by:

first accessing a local translation lookaside buffer;

when an address translation is not found in the local translation lookaside buffer, accessing a local virtual page table;

when the local virtual page table does not contain a local-physical-memory address for the page,

accessing one or more remote memories to find the page;

when the page is found in a remote memory,

moving the page from the remote memory to local, physical memory through a network interconnection and updating the virtual page table; and

when the page cannot be found in either local or remote memories,

accessing the logical backing store to find the page and move the page from the logical backing store to local physical memory, updating the virtual page table.

9. A method for extending a virtual address translation system of a local computer system to implement a logical, distributed memory, the method comprising:

when a valid virtual page table entry for a virtual page cannot be found, seeking a physical instantiation of the virtual page in one or more memories of remote computer systems;

when a physical instantiation of the virtual page is found in a memory of a remote computer system, moving the physical instantiation of the virtual page to local memory and updating the virtual page table; and

when a physical instantiation of the virtual page is not found in a memory of a remote computer system, moving the physical instantiation of the virtual page to local memory and updating the virtual page table.

10. The method of claim 9 further including collocating intercommunicating threads within a physical computer system in order to prevent thrashing within the logical, distributed memory.

11. Computer instructions encoded in a computer-readable memory that implement the method of claim 9.