Microprocessor having main processor and co-processor
First Claim
1. A microprocessor system for executing instructions described in a program, said system comprising:
- a main processor executing, by hardware, instructions which belong to a first instruction set and executing, by software, instructions which belong to a second instruction set, said main processor including an interrupt request reception circuit to encode an interrupt vector for said execution of an instruction of said second instruction set by using an interrupt handler, said interrupt request reception circuit generating an interrupt vector address corresponding to said interrupt vector; and
a co-processor operative under the control of said main processor autonomously fetching an instruction belonging to said second instruction set to execute same by hardware of said co-processor, said co-processor including an interrupt request generation circuit for decoding an interrupt request signal, said interrupt request generation circuit being connected to said interrupt request reception circuit by at least one signal line and said decoding allowing said interrupt vector address to be identified in said main processor.
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Accused Products
Abstract
There is provided a microprocessor system that can execute a specific set of instructions at a high speed while limiting the increase in size of the circuitry. The microprocessor system, which executes instructions described in a program, comprises a main processor which executes a first set of instructions by means of hardware and executes a second set of instructions by means of software and a co-processor which operates under the control of the main processor to execute the second set of instructions by means of hardware. When the co-processor encounters a specific instructions of the second set for which data under the control of the main processor needs to be operated, the co-processor issues a notification of this fact to the main processor to request it to execute the specific instruction. In this case, the co-processor updates its stack pointer and program counter by itself by means of hardware.
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Citations
35 Claims
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1. A microprocessor system for executing instructions described in a program, said system comprising:
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a main processor executing, by hardware, instructions which belong to a first instruction set and executing, by software, instructions which belong to a second instruction set, said main processor including an interrupt request reception circuit to encode an interrupt vector for said execution of an instruction of said second instruction set by using an interrupt handler, said interrupt request reception circuit generating an interrupt vector address corresponding to said interrupt vector; and a co-processor operative under the control of said main processor autonomously fetching an instruction belonging to said second instruction set to execute same by hardware of said co-processor, said co-processor including an interrupt request generation circuit for decoding an interrupt request signal, said interrupt request generation circuit being connected to said interrupt request reception circuit by at least one signal line and said decoding allowing said interrupt vector address to be identified in said main processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of processing computer programs, said method comprising:
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using a main processor executing hardware instructions which belong to a first instruction set and executing software instructions which belong to a second instruction set; using a co-processor, operative under the control of said main processor, for autonomously fetching instructions belonging to said second instruction set to execute the fetched instructions by hardware of said co-processor, wherein said co-processor is unable to execute at least one instruction in said second instruction set; and generating an interrupt request from said co-processor to said main processor when said co-processor detects encountering said at least one instruction belonging to said second instruction set which said co-processor cannot execute by itself, thereby requesting that said main processor execute said instruction, wherein said interrupt request comprises a signal on at least one signal line between said main processor and said co-processor dedicated to an interrupt vector signal, said interrupt vector comprising a dedicated interrupt vector component and a common interrupt request component, said dedicated interrupt vector component comprising a decoding for a specific interrupt handler to be executed by said main processor and said common interrupt request component providing an indication for a request for one of a plurality of other interrupt handlers to be specifically identified by additional information. - View Dependent Claims (20, 21)
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22. A microprocessor system, comprising:
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a main processor including an interrupt request reception circuit to encode an interrupt vector, said interrupt vector comprising a dedicated interrupt vector component and a common interrupt request component, said interrupt request reception circuit generating an interrupt vector address corresponding to said interrupt vector; a co-processor operative under the control of said main processor autonomously fetching and executing an instruction, said co-processor including an interrupt request generation circuit for decoding an interrupt request signal; and at least one signal line interconnecting said interrupt request generation circuit and said interrupt request reception circuit, wherein said dedicated interrupt vector component comprises a decoding for a specific interrupt handler to be executed by said main processor and said common interrupt request component provides an indication for a request for one of a plurality of interrupt handlers to be specifically identified by additional information. - View Dependent Claims (23)
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24. A microprocessor system for executing instructions described in a program, comprising:
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a main processor for executing by hardware those instructions which belong to a first instruction set and for executing by software those instructions which belong to a second instruction set; and a co-processor operative under a control of said main processor for autonomously fetching an instruction belonging to said second instruction set to execute the fetched instruction by hardware of the co-processor, wherein said coprocessor is provided with; a stack memory for holding data generated in a course of execution of an instruction which belongs to said second instruction set; a stack pointer for holding an address of most recent data in said stack memory; a program counter for holding an address of an instruction which is currently processed and belongs to said second instruction set; and an updating circuit for, in response to a detection of an encounter with a specific instruction among instructions belonging to said second instruction set for which data presently under the control of said main processor needs to be handled, issuing a notification of said encounter to said main processor to request the main processor to execute said specific instruction, and for updating said stack pointer for said stack memory in said coprocessor and said program counter in said coprocessor during an execution by said main processor. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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Specification