Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs

• US 7,202,132 B2
• Filed: 01/16/2004
• Issued: 04/10/2007
• Est. Priority Date: 01/16/2004
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Zhu, Huilong, Mocuta, Dan M.
• Primary Examiner(s): Huynh; Andy
• Assistant Examiner(s): Nguyen; Dao H.
• Application Number:
  US10/707,840
• Publication Number:
  US 20050156154A1
• Time in Patent Office: 1,180 Days
• Field of Search: 257/377, 438/299, 438/300
• US Class Current: 438/300
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

Claims

1. A method of fabricating a semiconductor structure, comprising the steps of:

forming a raised source region on a substrate;

forming a raised drain region on the substrate; and

forming a first silicon layer over the raised source region and a second silicon layer over the raised drain region,

wherein the first silicon layer formed over the raised source region and the second silicon layer over the raised drain region include cap portions and sidewall portions, the method further comprising a step of forming sacrificial spacers along the silicon sidewall portions.

2. A method according to claim 1, wherein the substrate includes a SiGe layer atop a buried oxide layer.

3. A method according to claim 1, further comprising a step of forming a gate stack on the substrate.

4. A method according to claim 3, further comprising a step of forming a trench isolation surrounding the gate stack, source region and drain region.

5. A method according to claim 1, further comprising a step of forming a first silicide contact on the first silicon layer.

6. A method according to claim 1, further comprising a step of forming a second suicide contact on the second silicon layer.

7. A method according to claim 1, wherein the first silicon layer is epitaxially formed silicon and the second silicon layer is epitaxially grown silicon.

8. A method according to claim 1, wherein the raised drain region is comprised of a strained silicon layer atop a SiGe layer.

9. A method according to claim 8, wherein the strained silicon layer is comprised of epitaxially grown silicon.

10. A method according to claim 1, wherein the raised source region is comprised of a strained silicon layer atop a SiGe layer.

11. A method according to claim 10, wherein the strained silicon layer is comprised of epitaxially grown silicon.

12. A method according to claim 1, further comprising steps of:

forming a third silicon layer over the cap of the first silicon layer over the raised source region; and

forming a fourth silicon layer over the cap of the second silicon layer over the raised drain region.

13. A method according to claim 12, further comprising a step of removing the sacrificial spacers.

14. A method according to claim 13, wherein the step of removing the sacrificial spacers includes etching away the sacrificial spacers.

15. A method of fabricating a semiconductor structure, comprising:

forming a raised source region on a substrate;

forming a raised drain region on the substrate;

forming a strained silicon layer on the raised source region and the raised drain region; and

forming a silicon cap on the strained silicon layer.

16. A method according to claim 15, further comprising forming silicon sidewalls on the raised source region and the raised drain region.

17. A method according to claim 16, further comprising forming sacrificial spacers along the silicon sidewalls.

18. A method according to claim 17, further comprising forming a silicon layer on the silicon cap.

19. A method according to claim 18, further comprising removing the sacrificial spacers.

20. A method according to claim 19, further comprising forming silicide contacts on the silicon layer.

21. A method comprising:

providing an SOI substrate having a patterned gate stack region comprising a gate dielectric formed on a surface thereof,

providing isolation structures on sides of the patterned gate stack region;

forming a gate stack on the gate dielectric;

forming spacers along gate sidewalls of the gate stack;

after spacer formation, forming raised source and drain regions comprising an SiGe layer;

forming a silicon layer on the SiGe layer of the raised source and drain regions, wherein the silicon layer has a smaller lattice constant than Ge such that the silicon layer is strained in tension; and

capping the raised drain region.

22. The method of claim 21, wherein the SOI substrate includes a buried oxide layer sandwiched between a top Si-containing layer and a bottom Si-containing layer.

23. The method of claim 22, wherein the top Si-containing layer and the bottom Si-containing layer comprise Si, SiGe, SiC, SiGeC, Si/Si or Si/SiGe.

24. The method of claim 21, wherein the SOI substrate is formed by bonding and cuffing processes or separation by implantation of oxygen (SIMOX) process.

25. The method of claim 21, further comprising forming a dielectric-capping layer on the gate stack comprising an oxide, nitride or oxynitride.

26. The method of claim 21, wherein the SiGe layer of the source and drain regions are selectively epitaxially grown.

27. The method of claim 21, wherein the SiGe layer of the source and drain regions are comprised, in whole or in part, of a top silicon-containing layer of the SOI substrate.

28. The method of claim 21, wherein a thickness for the strained Si layer on top of the SiGe layer is below a critical thickness.

29. The method of claim 28, wherein the critical thickness is a maximum thickness that the strained silicon layer can grow on the SiGe layer without forming defects in a crystal structure.

30. The method of claim 21, wherein the capping is formed from a silicon capping layer.

31. The method of claim 30, wherein the silicon capping layer is selectively epitaxially grown on the SiGe sidewalls of the raised drain region forming protective sidewalls.

32. The method of claim 30, further comprising forming oxide portions alongside the raised drain comprised of the SiGe layer and the strained Si layer.