Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials

• US 7,202,162 B2
• Filed: 04/22/2003
• Issued: 04/10/2007
• Est. Priority Date: 04/22/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Chao-Hsien, Lin, Jing-Cheng, Shue, Shau Lin, Liang, Mong Song
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US10/420,311
• Publication Number:
  US 20040214425A1
• Time in Patent Office: 1,449 Days
• Field of Search: 438637-640, 438/687, 438/685, 438/680
• US Class Current: 438/637
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal

Abstract

A process for improving the adhesion between an underlying copper structure, and overlying materials and structures, has been developed. The process features formation of a tantalum nitride layer on a copper structure, wherein the copper structure is located in a damascene type opening. To obtain the maximum adhesion benefit the tantalum nitride layer is formed via an atomic deposition layer procedure, performed at specific deposition conditions. The adhesion between the underlying copper structure and overlying materials such as a silicon nitride etch stop layer, as well the adhesion between the lower level copper structure and overlying upper level metal interconnect structures, is improved as a result of the presence of the atomic layer deposited tantalum nitride layer.

Claims

1. A method of forming metal interconnect network featuring a capping layer formed on an underlying lower level metal structure, comprising the steps of:

providing an underlying conductive region;

forming a first opening in a first dielectric layer disposed on said underlying conductive region exposing a portion of a top surface of said underlying conductive region;

forming a lower level metal structure in said first opening;

forming a capping layer on said lower level metal structure and directly on a top surface of said first dielectric layer;

forming a etch stop layer on said capping layer;

forming a second dielectric layer on said etch stop layer;

forming a second opening in said second dielectric layer, in said etch stop layer, and in said capping layer, exposing a portion of a top surface of said lower level metal structure; and

forming an upper level metal structure in said second opening.

2. The method of claim 1, wherein said conductive region is a metal via structure, comprised of either an aluminum based material, copper, or tungsten.

3. The method of claim 1, wherein said first dielectric layer is a low dielectric (low k) layer comprising a fluorinated silica glass (FSG) with a dielectric constant between 3.5 to 3.8 formed at a thickness between about 2000 to 4000 Angstroms via chemical vapor deposition procedures.

4. The method of claim 1, wherein said first dielectric layer is a silicon oxide layer, obtained via LPCVD or PECVD procedures at a thickness between about 2000 to 4000 Angstroms.

5. The method of claim 1, wherein said first opening is a damascene type opening, comprised with a diameter between about 0.05 to 0.3 um.

6. The method of claim 1, wherein said first opening is a dual damascene type opening.

7. The method of claim 1, wherein said lower level metal structure is comprised of copper, formed in said first opening via electro-chemical deposition procedures.

8. The method of claim 1, wherein said capping layer is a tantalum nitride layer, obtained via atomic layer deposition.

9. The method of claim 8, wherein said tantalum nitride layer is obtained at a thickness between about 10 to 150 Angstroms, and with a N/Ta ratio greater than 1.2, with a preferred ratio of 1.5.

10. The method of claim 1, wherein said capping layer is obtained via ALD procedures, performed at a temperature between about 175 to 350°

C., at a pressure between about 50 to 500 torr, using a ratio of PDMAT or TaCl₂ to ammonia between about 0.1 to 1, to 1 to 1.

11. The method of claim 1, wherein said etch stop layer is a silicon nitride layer, obtained via LPCVD or PECVD procedures to a thickness between about 300 to 500 Angstroms.

12. The method of claim 1, wherein said etch stop layer is a silicon carbide layer, obtained at a thickness between about 300 to 500 Angstroms.

13. The method of claim 1, wherein said second dielectric layer is a low dielectric (low k) layer comprising a fluorinated silica glass (FSG) with a dielectric constant between 3.5 to 3.8 formed at a thickness between about 2000 to 4000 Angstroms via chemical vapor deposition procedures.

14. The method of claim 1, wherein said second dielectric layer is a silicon oxide layer, obtained via LPCVD or PECVD procedures at a thickness between about 2000 to 4000 Angstroms.

15. A method of fabricating a metal interconnect network, comprising the steps of:

providing an underlying conductive region;

forming a first low dielectric layer;

forming a first opening in said first low dielectric layer exposing a portion of a top surface of said conductive region;

forming a lower level copper structure, completely filling said first opening;

performing an atomic layer deposition (ALD) procedure to form a TaN layer on a top surface of said lower level copper structure and directly on a top surface of said first low dielectric layer;

forming an etch stop layer on said TaN layer;

forming a second low dielectric layer on said etch stop layer;

forming a second opening in said second low dielectric layer, in said etch stop layer, and in said TaN layer, exposing a portion of a top surface of said lower level copper structure; and

forming an upper level metal structure in said second opening.

16. The method of claim 15, wherein said first low dielectric layer is fluorinated silica glass (FSG), layer, comprised with a dielectric constant between 3.5 to 3.8, and formed at a thickness between about 2000 to 4000 Angstroms, via chemical vapor deposition procedures.

17. The method of claim 15, wherein said first opening is a damascene type opening, comprised with a diameter between about 0.05 to 0.3 um.

18. The method of claim 15, wherein said first opening is a dual damascene type opening.

19. The method of claim 15, wherein said lower level copper structure is obtained via electrochemical deposition procedures to a thickness between about 3,000 to 30,000 Angstroms.

20. The method of claim 15, wherein said TaN layer is formed at a thickness between about 10 to 150 Angstroms, with a N/Ta ratio greater than 1.2, with a preferred ratio of 1.5.

21. The method of claim 15, wherein the said ALD procedure is performed at a temperature between about 175 to 350°

C., at a pressure between about 50 to 500 torr, using a ratio of PDMAT to TaCl₂ to ammonia between about 0.1 to 1, to 1 to 1.

22. The method of claim 15, wherein said etch stop layer is a silicon nitride layer, obtained via LPCVD or PECVD procedures to a thickness between about 300 to 500 Angstroms.

23. The method of claim 15, wherein said etch stop layer is a silicon carbide layer, obtained at a thickness between about 300 to 500 Angstroms.

24. The method of claim 15, wherein said second low dielectric layer is a fluorinated silica glass (FSG), with a dielectric constant between 3.5 to 3.8, formed at a thickness between about 2000 to 4000 Angstroms, via chemical vapor deposition procedures.