FINFET including a superlattice

• US 7,202,494 B2
• Filed: 06/28/2006
• Issued: 04/10/2007
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Blanchard, Richard A., Rao, Kalipatnam Vivek, Kreps, Scott A.
• Primary Examiner(s): Huynh; Andy
• Assistant Examiner(s): Nguyen; Thinh T
• Application Number:
  US11/426,969
• Publication Number:
  US 20060292889A1
• Time in Patent Office: 286 Days
• Field of Search: 257/9, 257/15, 257/18, 257/19, 257/22, 257/28, 257/E33.09
• US Class Current: 257/9
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Claims

1. A semiconductor device comprising:

at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of said fin, and a gate overlying said fin;

said fin comprising at least one superlattice including a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2. The semiconductor device of claim 1 further comprising a substrate supporting said at least one FINFET;

and wherein said fin comprises a pair of spaced apart superlattices and a semiconductor layer therebetween with groups of layers of each superlattice being stacked in a lateral direction.

3. The semiconductor device of claim 1 further comprising a substrate supporting said at least one FINFET;

and wherein said fin comprises a single superlattice with groups of layers stacked in a vertical direction.

4. The semiconductor device of claim 1 wherein said substrate comprises an uppermost insulator layer supporting said at least one FINFET.

5. The semiconductor device of claim 1 wherein said gate comprises a gate dielectric layer and a gate electrode layer overlying said gate dielectric layer.

6. The semiconductor device of claim 1 wherein at least one group of layers of said at least one superlattice is substantially undoped.

7. The semiconductor device of claim 1 wherein said base semiconductor comprises silicon.

8. The semiconductor device of claim 7 wherein said at least one non-semiconductor monolayer comprises oxygen.

9. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen.

10. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer is a single monolayer thick.

11. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

12. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

13. The semiconductor device of claim 1 wherein opposing base semiconductor portions in adjacent groups of layers of said at least one superlattice are chemically bound together.

14. The semiconductor device of claim 1 wherein said at least one FINFET comprises a plurality of FINFETS.

15. The semiconductor device of claim 14 wherein said plurality of FINFETS have different channel conductivities.

16. The semiconductor device of claim 1 wherein said at least one FINFET comprises at least one n-channel FINFET and at least one p-channel FINFET.

17. The semiconductor device of claim 1 wherein said at least one FINFET comprises a plurality thereof defining an inverter.

18. A semiconductor device comprising:

a substrate; and

at least one fin field-effect transistor (FINFET) supported by said substrate and comprising a fin, source and drain regions adjacent opposite ends of said fin, and a gate overlying said fin;

said fin comprising a pair of spaced apart superlattices and a semiconductor layer therebetween;

each superlattice comprising a plurality of groups of layers stacked in a lateral direction, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

19. The semiconductor device of claim 18 wherein said substrate comprises an uppermost insulator layer supporting said at least one FINFET.

20. The semiconductor device of claim 18 wherein said at least one FINFET comprises a plurality of FINFETS having different channel conductivities.

21. A semiconductor device comprising:

a substrate; and

at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of said fin, and a gate overlying said fin;

said fin comprising a superlattice including a plurality of groups of layers stacked in a vertical direction, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

22. The semiconductor device of claim 21 wherein said substrate comprises an uppermost dielectric layer supporting said at least one FINFET.

23. The semiconductor device of claim 21 wherein said at least one FINFET comprises a plurality of FINFETS having different channel conductivities.