Construction of thin strain-relaxed SiGe layers and method for fabricating the same

• US 7,202,512 B2
• Filed: 08/11/2004
• Issued: 04/10/2007
• Est. Priority Date: 02/17/2004
• Status: Expired due to Fees

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Liu, Chee-Wee, Chen, Pang-Shiu, Chen, Lih-Juann, Liao, Kao-Feng, Lee, Sheng-Wei
• Primary Examiner(s): Baumeister; B. William
• Assistant Examiner(s): Reames; Matthew L.
• Application Number:
  US10/915,362
• Publication Number:
  US 20050179028A1
• Time in Patent Office: 972 Days
• Field of Search: 257/19, 257/190
• US Class Current: 257/190
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02447 Silicon carbide
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions

Abstract

A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.

Claims

1. A construction of a thin strain-relaxed SiGe layers, comprising:

an semiconductor substrate;

a buffer layer formed on the semiconductor substrate and including Si and Ge;

a Si(C) layer formed on the buffer layer, the buffer layer providing an in-plane lattice match between the buffer layer and the Si(C) layer, serving as a trapping center for misfit dislocations and suppressing the propagation of threading dislocations; and

an epitaxial layer formed on the Si(C) layer and including Si and Ge, the Ge content in the buffer layer and the epitaxial layer being the same, the thickness of the epitaxial layer being thicker than the buffer layer, and the lattice constant of the Si(C) layer being smaller than that of the buffer layer and epitaxial layer.

12. The construction of claim 1, wherein the thickness of the buffer layer is thinner than a critical thickness of the buffer layer.

13. The construction of claim 1, wherein a concentration of Ge in the epitaxial SiGe layer is the same or larger than that of the buffer layer.

2. A fabricating method of a thin strain-relaxed SiGe layers, comprising steps of:

providing an semiconductor substrate;

forming a buffer layer on the semiconductor substrate, the buffer layer including Si and Ge;

forming a Si(C) layer on the buffer layer, the buffer layer providing an in-plane lattice match between the buffer layer and the Si(C) layer, serving as a trapping center for misfit dislocations and suppressing the propagation of threading dislocations;

forming an epitaxial layer on the Si(C) layer, the epitaxial layer including Si and Ge, the Ge content in the buffer layer and the epitaxial layer being the same, the thickness of the epitaxial layer being thicker than the buffer layer, and the lattice constant of the Si(C) layer being smaller than that of the buffer layer and epitaxial layer; and

annealing the epitaxial layer.

3. The method of claim 2 further comprises a step of annealing the epitaxial layer.

4. The method of claim 2, wherein the epitaxial layer is formed by the ultra-high vacuum chemical vapor deposition.

5. The method of claim 2, wherein the epitaxial layer is formed by the molecule beam epitaxy growth method.

6. The method of claim 2, wherein the epitaxial layer is formed by the low pressure chemical vapor deposition (LPCVD).

7. The method of claim 2, wherein the epitaxial layer is formed by the rapid thermal chemical vapor deposition.

8. The method of claim 2, wherein the epitaxial layer is formed by a method which can fabricate the SiGe(C) epitaxial alloys.

9. The method of claim 2, wherein the thickness of the buffer SiGe layer is thinner than a critical thickness of the buffer SiGe layer.

10. The method of claim 2, wherein the concentration of Ge in the epitaxial SiGe layer is the same, or larger than that of the buffer SiGe layer.

11. The method of claim 2, wherein the epitaxial layer, the Si(C) layer, and the buffer layer are formed by a method to fabricate the SiGe(C) epitaxial alloys.