Trench MOSFET with trench tip implants

• US 7,202,525 B2
• Filed: 02/28/2005
• Issued: 04/10/2007
• Est. Priority Date: 03/01/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M.
• Primary Examiner(s): Andujar; Leonardo
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US11/081,893
• Publication Number:
  US 20050224870A1
• Time in Patent Office: 771 Days
• Field of Search: None
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power semiconductor device includes a channel region atop an epitaxially silicon layer and a plurality of shallow gate electrode trenches within the channel region such that the bottom of each trench extends to a distance above the junction defined by the channel region and epitaxially silicon layer. Formed at the bottom of each trench within the channel region are trench tip implants of the same conductivity as the epitaxial silicon layer. The trench tip implants extend through the channel region and into the epitaxially silicon layer. The tips effectively pull up the drift region of the device in a localized fashion. In addition, an insulation layer lines the sidewalls and bottom of each trench such that the insulation layer is thicker along the trench bottoms than along the trench sidewalls. Among other benefits, the shallow trenches, trench tips, and variable trench insulation layer allow for reduced on-state resistance and reduced gate-to-drain charge.

Claims

1. A power semiconductor device, comprising:

a semiconductor body of a first conductivity type;

a channel region of a second conductivity type in said semiconductor body and extending to a first depth within said semiconductor body;

a plurality of trenches along a surface of said semiconductor body, said trenches extending into said channel region to a depth above said first depth, each trench including sidewalls and a bottom;

a tip implant of said first conductivity type formed within said channel region at the bottom of each trench and extending through said channel region beyond said first depth and into said semiconductor body; and

a gate electrode within each of said plurality of trenches;

wherein each of said tip implants has a concentration that is low enough such that said tip implants deplete out when reversed biased and that is high enough so as to not form a JFET.

2. The power semiconductor device of claim 1, wherein said plurality of trenches each extend to a depth that is approximately 0.1 um or greater above said first depth.

3. The power semiconductor device of claim 1, further comprising an insulation layer lining the bottom and sidewalls of each of said plurality of trenches, wherein said insulation layer is thicker along the bottom of each trench than along the sidewalls of each trench.

4. The power semiconductor device of claim 3, wherein said insulation layer along the bottom of each trench is 1.5 to 4 times thicker than said insulation layer along the sidewalls of each trench.

5. The power semiconductor device of claim 1, further comprising a plurality of source regions of said first conductivity type within said channel region, each of said source regions being adjacent to one of said plurality of trenches.

6. The power semiconductor device of claim 5, wherein each of said plurality of source regions overlaps said gate electrode within said adjacent trench by approximately 500 A or more.

7. The power semiconductor device of claim 6,

wherein each of said gate electrodes is recessed below a top surface of said semiconductor body by approximately 2000 A.

8. The power semiconductor device of claim 5, further comprising a plurality of contact regions of said second conductivity along the surface of said semiconductor body between adjacent source regions and adjacent trenches.

9. The power semiconductor device of claim 8, further comprising:

a termination trench in said semiconductor body, said termination trench including a side wall and bottom and defining an active area that includes said plurality of trenches;

a field insulation body over said sidewall and said bottom of said termination trench; and

a termination electrode in said termination trench overlying said field insulation body and extending towards said active area.

10. The power semiconductor device of claim 9, further comprising an insulation body atop each of said gate electrodes, each insulation body extending above the surface of said semiconductor body and covering a portion of said source regions adjacent to the trench corresponding to said insulation body.

11. A method for fabricating a power semiconductor device, comprising the steps of:

etching a plurality of trenches in a semiconductor body comprising an epitaxial silicon layer of a first conductivity and a channel region of a second conductivity formed atop said epitaxial silicon layer and extending to a first depth within said semiconductor body, wherein each of said plurality of trenches extends into said channel region to a depth above said first depth, each trench including sidewalls and a bottom;

for each trench forming spacers substantially along the sidewalls, growing a first insulation layer on the bottom, removing said spacers from the sidewalls, growing a second insulation layer along the sidewalls and bottom thereby forming a resulting insulation layer that is thicker along the bottom than along the sidewalls;

forming a tip implant of said first conductivity type within said channel region at the bottom of each trench such that each tip implant extends through said channel region beyond said first depth and into said epitaxial silicon layer; and

forming a gate electrode within each of said plurality of trenches;

wherein each of said tip implants has a concentration that is low enough such that said tip implants deplete out when reversed biased and that is high enough so as to not form a JFET.

12. The method of claim 11, wherein said plurality of trenches each extend to a depth that is approximately 0.1 um or greater above said first depth.

13. The method of claim 11, wherein said resulting insulation layer along the bottom of each trench is 1.5 to 4 times thicker than said resulting insulation layer along the sidewalls of each trench.

14. The method of claim 11, further comprising the step of forming a plurality of source regions of said first conductivity type within said channel region such that each source region is adjacent to one of said plurality of trenches.

15. The method of claim 14, wherein each of said plurality of source regions overlaps said gate electrode within said adjacent trench by approximately 500 A or more.

16. The method of claim 14, further comprising the step of forming a plurality of contact regions of said second conductivity within said channel region between adjacent source regions and adjacent trenches.

19. The method of claim 16, further comprising, prior to forming said plurality of source regions, the step of forming an insulation body atop each of said gate electrodes, each insulation body extending above the surface of said semiconductor body and covering portions of subsequently formed said plurality of source regions that are adjacent to the trench corresponding to said insulation body.

17. A method for fabricating a power semiconductor device, comprising the steps of:

etching a plurality of trenches in a semiconductor body comprising an epitaxial silicon layer of a first conductivity and a channel region of a second conductivity formed atop said epitaxial silicon layer and extending to a first depth within said semiconductor body, wherein each of said plurality of trenches extends into said channel region to a depth above said first depth, each trench including sidewalls and a bottom;

forming a tip implant of said first conductivity type within said channel region at the bottom of each trench such that each tip implant extends through said channel region beyond said first depth and into said epitaxial silicon layer;

etching doped polysilicon within each of said plurality of trenches until the doped polysilicon is recessed below a top surface of said semiconductor body by approximately 2000 A, thereby forming a gate electrode within each of said plurality of trenches; and

forming a plurality of source regions of said first conductivity type within said channel region such that each source region is adjacent to one of said plurality of trenches;

wherein each of said plurality of source regions overlaps said gate electrode within said adjacent trench by approximately 500 A or more.

18. A method for fabricating a power semiconductor device, comprising the steps of:

etching a plurality of trenches in a semiconductor body comprising an epitaxial silicon layer of a first conductivity and a channel region of a second conductivity formed atop said epitaxial silicon layer and extending to a first depth within said semiconductor body, wherein each of said plurality of trenches extends into said channel region to a depth above said first depth, each trench including sidewalls and a bottom;

for each trench forming spacers substantially along the sidewalls, growing a first insulation layer on the bottom, removing said spacers from the sidewalls, growing a second insulation layer along the sidewalls and bottom thereby forming a resulting insulation layer that is thicker along the bottom than along the sidewalls;

forming a tip implant of said first conductivity type within said channel region at the bottom of each trench such that each tip implant extends through said channel region beyond said first depth and into said epitaxial silicon layer; and

forming a gate electrode within each of said plurality of trenches;

forming a plurality of source regions of said first conductivity type within said channel region such that each source region is adjacent to one of said plurality of trenches;

forming a plurality of contact regions of said second conductivity within said channel region between adjacent source regions and adjacent trenches;

etching a termination trench in said semiconductor body prior to etching said plurality of trenches, said termination trench including a side wall and bottom and defining an active area that includes said plurality trenches;

forming a field insulation body over said sidewall and said bottom of said termination trench; and

forming a termination electrode over said field insulation body and extending towards said active area.