Wafer bonding of micro-electro mechanical systems to active circuitry

• US 7,202,560 B2
• Filed: 12/15/2004
• Issued: 04/10/2007
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies Wireless IP Singapore Pte Limited (Broadcom, Inc.)
• Inventors: Dungan, Thomas E., Fazzio, Ronald S.
• Primary Examiner(s): Nhu; David
• Application Number:
  US11/012,589
• Publication Number:
  US 20060128058A1
• Time in Patent Office: 846 Days
• Field of Search: 257/678, 257/296, 257/680, 257/690, 257/704, 257/710, 257/713, 257/724, 257/778, 257/781, 257/782
• US Class Current: 257/713
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H03H 9/0547 consisting of a vertical arrangement H03H9/0566 takes precedence

Abstract

A single integrated wafer package includes a micro electromechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS component on its first surface. The active device wafer has a first surface and includes an active device circuit on its first surface. The seal ring is adjacent the first surface of the MEMS wafer such that a seal is formed about the MEMS component. An external contact is provided on the wafer package. The external contact is accessible externally to the wafer package and is electrically coupled to the active device circuit of the active device wafer.

Claims

1. A single integrated wafer package comprising:

a micro electromechanical system (MEMS) wafer with a first surface, the MEMS wafer having at least one MEMS component on its first surface;

an active device wafer with a first surface, the active device wafer having an active device circuit on its first surface and configured to be spaced apart from the MEMS wafer such that the first surface of the MEMS wafer faces the first surface of the active device wafer;

a seal ring adjacent the first surface of the MEMS wafer such that a seal is formed about the MEMS component by at least the combination of the seal ring and the first surface of the MEMS wafer; and

an external contact to the single integrated wafer package, wherein the external contact accessible externally to the single integrated wafer package and is electrically coupled to the active device circuit of the active device wafer.

2. The single integrated wafer package of claim 1, wherein the seal formed about the MEMS component comprises a hermetic seal.

3. The single integrated wafer package of claim 1, wherein the MEMS component is one of a group comprising a thin film acoustic resonator (FBAR) and a solidly mounted acoustic resonator (SMR).

4. The single integrated wafer package of claim 1, wherein the seal ring is also adjacent the first surface the active device wafer such that the seal is formed by the combination of the seal ring, the first surface the active device wafer, and first surface the MEMS wafer.

5. The single integrated wafer package of claim 4, wherein the formed seal is a hermetic seal.

6. The single integrated wafer package of claim 4, wherein the seal ring between the MEMS wafer and the active device wafer is a copper pillar ring surrounding the MEMS component and that couples the wafers together such that they form a single integrated component.

7. The single integrated wafer package of claim 1, wherein the MEMS wafer further includes at least one via through which an electrical connection is made between the external contact and at least one of the group comprising the active device circuit and the MEMS component.

8. The single integrated wafer package of claim 1, wherein the active device wafer further includes at least one via through which an electrical connection is made between the external contact and at least one of the group comprising the active device circuit and the MEMS component.

9. The single integrated wafer package of claim 7, wherein at least one column is formed between the MEMS wafer and the active device wafer, the column aligned with the via such that the column facilitates the electrical connection between the active device circuit and the external contact.

10. The single integrated wafer package of claim 8, wherein at least one column is formed between the MEMS wafer and the active device wafer, the column aligned with the via such that the column facilitates the electrical connection between the MEMS wafer and the external contact.

11. A single integrated wafer package comprising:

a micro electromechanical system (MEMS) wafer with a first surface, the MEMS wafer having at least one MEMS component on its first surface;

an active device wafer with a first surface, the active device wafer having an active device circuit on its fist surface;

a seal ring adjacent the first surface of the MEMS wafer such that a seal is formed about the MEMS component;

an external contact to the single integrated wafer package, wherein the external contact accessible externally to the single integrated wafer package and is electrically coupled to the active device circuit of the active device wafer; and

a microcap wafer coupled between the MEMS wafer and the active device wafer, and wherein the seal ring is sandwiched between the MEMS wafer and the microcap wafer thereby providing the seal about the MEMS component.

12. The single integrated wafer package of claim 11, wherein the seal formed about the MEMS component comprise a hermetic seal.

13. The single integrated wafer package of claim 11 wherein the MEMS wafer further includes at least one via through which an electrical connection is made between the external contact and at least one of the group comprising the active device circuit and the MEMS component.

14. The single integrated wafer package of claim 11 wherein the active device wafer further includes at least one via through which an electrical connection is made between the external contact and at least one of the group comprising the active device circuit and the MEMS component.