Voltage tolerant input buffer
First Claim
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1. A buffer circuit comprising:
- a differential circuit, the differential circuit comprising a first differential transistor pair and a second differential transistor pair, the first differential transistor pair and the second differential transistor pair being complementary; and
a plurality of switches coupled with the differential circuit;
wherein the plurality of switches apply a voltage to the differential circuit in a first state and isolate the differential circuit from the voltage in a second state, the voltage being at a higher potential in the second state than in the first state, and wherein the buffer circuit is to operate in both the first state and the second state.
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Abstract
A method and an apparatus are described for a voltage tolerant input buffer. An embodiment of an input buffer includes a differential circuit and a plurality of switches coupled with the differential circuit. The plurality of switches applies a voltage to the differential circuit in a first state and isolate the differential circuit from the voltage in a second state.
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Citations
18 Claims
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1. A buffer circuit comprising:
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a differential circuit, the differential circuit comprising a first differential transistor pair and a second differential transistor pair, the first differential transistor pair and the second differential transistor pair being complementary; and a plurality of switches coupled with the differential circuit; wherein the plurality of switches apply a voltage to the differential circuit in a first state and isolate the differential circuit from the voltage in a second state, the voltage being at a higher potential in the second state than in the first state, and wherein the buffer circuit is to operate in both the first state and the second state. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An input buffer comprising:
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a first differential transistor pair; a first current source coupled with the first differential transistor pair; a second differential transistor pair, the second differential transistor pair being complementary to the first differential transistor pair; a second current source, the second current source being coupled with the second differential transistor pair; and one or more switches, the one or more switches to turn on the first current source when a voltage source is at a first voltage and to turn off the first current source when the voltage source is at a second voltage, the second voltage being higher than the first voltage; wherein the input buffer is to operate at both the first voltage and the second voltage. - View Dependent Claims (8, 9, 10, 11)
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12. A method comprising:
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receiving an enable signal for an I/O (input/output) system input buffer; providing a power supply voltage to the input buffer when the enable signal is active; separating the input buffer from the power supply voltage when the enable signal is inactive; and performing I/O operations when the enable signal is active and when the enable signal is inactive. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A buffer circuit comprising:
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a differential circuit, the differential circuit comprises a first differential transistor pair and a second differential transistor pair, the first differential transistor pair and the second differential transistor pair being complementary; a plurality of switches coupled with the differential circuit, wherein the plurality of switches are to apply a voltage to the differential circuit in a first state and isolate the differential circuit from the voltage in a second state; and an input/output (I/O) pad coupled with a transistor, the transistor providing a signal from the input/output pad to a tail node and an output node of the first differential transistor pair and the second differential transistor pair in the second state.
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Specification