Device and method for compensating defect in semiconductor memory
First Claim
1. A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, said device comprising:
- a memory array, comprising at least a defectless sub-memory region, said memory array being coupled to an address decoder circuit and a sensing circuit for storing data;
a selection circuit, coupled to a control unit, outputting a selection signal to said control unit; and
a first input address buffer, coupled to said control unit and the address decoder circuit, outputting an address signal to said address decoder circuit in response to said selection signal for selecting said defectless sub-memory region to store data.
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Abstract
A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.
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Citations
12 Claims
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1. A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, said device comprising:
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a memory array, comprising at least a defectless sub-memory region, said memory array being coupled to an address decoder circuit and a sensing circuit for storing data; a selection circuit, coupled to a control unit, outputting a selection signal to said control unit; and a first input address buffer, coupled to said control unit and the address decoder circuit, outputting an address signal to said address decoder circuit in response to said selection signal for selecting said defectless sub-memory region to store data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, said semiconductor memory including a memory region to store data and an address input port for inputting an address signal, said memory region further including at least a defectless sub-memory region, said address signal determining a location of said data in said memory region, said method comprising:
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determining whether or not said memory region of said semiconductor memory has a defect; and replacing said memory region with said defectless sub-memory region to store said data when said semiconductor memory is defective. - View Dependent Claims (11, 12)
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Specification