Segmented MRAM memory array

• US 7,203,129 B2
• Filed: 02/16/2004
• Issued: 04/10/2007
• Est. Priority Date: 02/16/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lai, Li-Shyue, Lin, Wen-Chin, Tang, Danny D.
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): Sofocleous; Alexander
• Application Number:
  US10/780,171
• Publication Number:
  US 20050180203A1
• Time in Patent Office: 1,149 Days
• Field of Search: 365/148, 365/242, 365/243, 365/130, 365/170, 365/171, 365/172, 365/230.03, 365/158, 365/173, 365/175
• US Class Current: 365/243
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device

Abstract

In one example, an MRAM memory array includes a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of first and second diodes, and magnetic tunnel junction memories. Each first diode includes a cathode, and an anode coupled to each bit line. Each second diode includes an anode, and a cathode coupled to each word line. The magnetic tunnel junction memories include a pinned layer, a free layer, and a non-magnetic layer. The non-magnetic layer is located between the pinned layer and the free layer. Each diode is positioned at crossing points of the bit lines and the word lines and connected between the first diode at the corresponding crossing bit line and the second diode at the corresponding crossing word line.

Claims

1. An MRAM memory array, comprising:

word lines;

bit lines crossing the word lines;

first diodes, each first diode comprising;

a cathode; and

an anode coupled to a corresponding bit line;

second diodes, each second diode comprising;

an anode; and

a cathode coupled to a corresponding word line; and

magnetic tunnel junction memories including;

a pinned layer;

a free layer; and

a non-magnetic layer located between the pinned layer and the free layer;

each magnetic tunnel junction memory being positioned at a crossing point of a bit line and a word line, each magnetic tunnel junction memory being connected between a first diode at a corresponding crossing bit line and a second diode at a corresponding crossing word line.

2. The MRAM memory array as claimed in claim 1, wherein the number of diodes is equal to the total number of word lines and bit lines.

3. The MRAM memory array as claimed in claim 1, wherein the number of magnetic tunnel junction memories is the product of the number of word lines and the number of bit lines.

4. The MRAM memory array as claimed in claim 1, wherein the numbers of word lines is three and the numbers of the bit lines is two.

5. The MRAM memory array as claimed in claim 1, wherein the numbers of word lines is three and the number of bit lines is three.

6. An MRAM memory array, comprising:

a first word line;

a second word line;

a third word line;

a first bit line crossing the first word line, the first bit line further crossing the second word line;

the first bit line further crossing the third word line;

a second bit line crossing the first word line, the second bit line further crossing the second word line;

the second bit line further crossing the third word line;

a first diode having a first cathode, and a first anode coupled to the first bit line;

a second diode having a second cathode, and a second anode coupled to the second bit line;

a third diode having a third anode, and a third cathode coupled to the first word line;

a fourth diode having a fourth anode, and a fourth cathode coupled to the second word line;

a fifth diode having a fifth anode, and a fifth cathode coupled to the third word line;

a first magnetic tunnel junction memory connected between the first cathode and the third anode, the first magnetic tunnel junction memory including;

a first pinned layer;

a first free layer; and

a first non-magnetic layer located between the first pinned layer and the first free layer;

the first magnetic tunnel junction memory being positioned at a crossing point of the first bit line arid the first word line;

a second magnetic tunnel junction memory connected between the second cathode and the third anode, the second magnetic tunnel junction memory including;

a second pinned layer;

a second free layer; and

a second non-magnetic layer located between the second pinned layer and the second free layer;

the second magnetic tunnel junction memory being positioned at crossing point of the second bit line and the first word line;

a third magnetic tunnel junction memory connected between the first cathode and the fourth anode, the third magnetic tunnel junction memory including;

a third pinned layer;

a third free layer; and

a third non-magnetic layer located between the third pinned layer and the third free layer;

the third magnetic tunnel junction memory being positioned at crossing point of the first bit line and the second word line;

a fourth magnetic tunnel junction memory connected between the second cathode and the fourth anode, the fourth magnetic tunnel junction memory including;

a fourth pinned layer;

a fourth free layer; and

a fourth non-magnetic layer located between the fourth pinned layer and the fourth free layer;

the fourth magnetic tunnel junction memory being positioned at crossing point of the second bit line and the second word line;

a fifth magnetic tunnel junction memory connected between the first cathode and the fifth anode, the fifth magnetic tunnel junction memory including;

a fifth pinned layer;

a fifth free layer; and

a fifth non-magnetic layer located between the fifth pinned layer and the fifth free layer;

the fifth magnetic tunnel junction memory being positioned at crossing point of the first bit line and the third word line; and

a sixth magnetic tunnel junction memory connected between the second cathode and the fifth anode, the sixth magnetic tunnel junction memory including;

a sixth pinned layer;

a sixth free layer; and

a sixth non-magnetic layer located between the sixth pinned layer and the sixth free layer;

the sixth magnetic tunnel junction memory being positioned at crossing point of the second bit line and the third word line.

7. An MRAM memory array comprising:

a plurality of word and bit lines;

a plurality of first and second diodes, wherein each of the first diodes comprising a cathode and an anode that couples to a corresponding bit line and each of the second diodes comprising an anode and a cathode that couples to a corresponding word line; and

a plurality of magnetic tunnel junction memories each positioned where one of the first conductive lines crosses one of the second conductive lines, wherein each of the plurality of magnetic tunnel junction memories is connected between a first diode at the corresponding bit line and a second diode at the corresponding word line.

8. The MRAM memory array of claim 7 wherein each magnetic tunnel junction memories includes a pinned layer, a free layer, and a non-magnetic layer located between the pinned layer and the free layer.

9. The MRAM memory array of claim 7 wherein a total number of first and second diodes is equal to a total number of word and bit lines.

10. The MRAM memory array of claim 7 wherein a total number of the magnetic tunnel junction memories is a product of a total number of word lines and a total number of the bit lines.

11. The MRAM memory array of claim 7 further comprising a plurality of segments, wherein each segment includes at least two of the plurality of magnetic tunnel junction memories.

12. The MRAM memory array of claim 11 wherein the segments are separated by diodes.