System and method for switching asynchronous transfer mode cells
First Claim
1. An asynchronous transfer mode switch, comprising:
- a plurality of input/output ports for receiving and transmitting ATM cells;
a cell header filter for decoding ATM cell headers to determine each cell'"'"'s ATM channel;
at least one processor for manipulating each ATM cell in response to the ATM channel identified by the cell header filter and outputting each of the manipulated ATM cells on one of the input/output ports; and
at least one memory structure associated with the at least one processor for storing ATM cell data prior to transmission on one of the input/output ports,wherein each available ATM channel is represented by a flow data structure in the at least one memory structure, the flow data structure including a plurality of state variables associated with the ATM channel and further including memory addresses for a cell reception handler routine and a cell transmission handler routine, wherein the plurality of state variables include at least one variable selected from the group consisting of the following information;
static parameters such as the ATM channel'"'"'s output port, priority and cell header rewriting rules, a memory address to a queue of buffered cells awaiting transmission;
the ATM channel'"'"'s early packet discard/partial packet discard state, and channel statistics such as a count of cells passing through the channel.
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Accused Products
Abstract
One embodiment of a method for switching ATM cells using Early Packet Discard and Partial Packet Discard is provided. Initially, a first cell of an AAL5 packet is received at an input port. Next, it is determined whether there is likely to be enough buffering available to handle the whole packet (i.e., up to 64 Kbytes). If it is determined that sufficient buffering is unlikely to be available, the entire packet is discarded. If it is determined that sufficient buffering exists, the cell is received and buffered for subsequent transmission. Next it is determined whether the flow'"'"'s buffer is filled at any time after initial transmission of a AAL5 cell but before reception of the final cell. If such a state is determined, the current cell is discarded and a flag is set in the flow structure so that subsequent cells of the same packet, except the last, will also be discarded.
42 Citations
23 Claims
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1. An asynchronous transfer mode switch, comprising:
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a plurality of input/output ports for receiving and transmitting ATM cells; a cell header filter for decoding ATM cell headers to determine each cell'"'"'s ATM channel; at least one processor for manipulating each ATM cell in response to the ATM channel identified by the cell header filter and outputting each of the manipulated ATM cells on one of the input/output ports; and at least one memory structure associated with the at least one processor for storing ATM cell data prior to transmission on one of the input/output ports, wherein each available ATM channel is represented by a flow data structure in the at least one memory structure, the flow data structure including a plurality of state variables associated with the ATM channel and further including memory addresses for a cell reception handler routine and a cell transmission handler routine, wherein the plurality of state variables include at least one variable selected from the group consisting of the following information;
static parameters such as the ATM channel'"'"'s output port, priority and cell header rewriting rules, a memory address to a queue of buffered cells awaiting transmission;
the ATM channel'"'"'s early packet discard/partial packet discard state, and channel statistics such as a count of cells passing through the channel. - View Dependent Claims (2, 3)
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4. A method for switching asynchronous transfer mode cells, comprising the steps of:
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receiving an ATM cell at an input port; identifying an ATM flow associated with the received ATM cell, wherein the ATM flow includes at least memory addresses for an cell reception handler routine and a cell transmission handler routine; reading the contents of the ATM flow into a plurality of registers, including reading the memory address for the cell reception handler routine into a program counter register for immediate execution; determining whether the received ATM cell is subject to retransmission; and performing the following steps if it is determined that the received ATM cell is subject to retransmission; allocating a cell buffer; copying the cell contents from the input port to the allocated buffer; determining whether a circular array of buffer pointers associated with the identified ATM flow is full; and placing a pointer to the cell buffer into the circular array if it is determined that the circular array is not full. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A computer readable medium incorporating instructions for switching asynchronous transfer mode cells, the instructions comprising:
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one or more instructions for receiving an ATM cell at an input port; one or more instructions for identifying an ATM flow associated with the received ATM cell, wherein the ATM flow includes at least memory addresses for an cell reception handler routine and a cell transmission handler routine; one or more instructions for reading the contents of the ATM flow into a plurality of registers, including reading the memory address for the cell reception handler routine into a program counter register for immediate execution; one or more instructions for determining whether the received ATM cell is subject to retransmission; and performing the following instructions if it is determined that the received ATM cell is subject to retransmission; one or more instructions for allocating a cell buffer; one or more instructions for copying the cell contents from the input port to the allocated buffer; one or more instructions for determining whether a circular array of buffer pointers associated with the identified ATM flow is full; and one or more instructions for placing a pointer to the cell buffer into the circular array if it is determined that the circular array is not full. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification