Methods and apparatus for signal modification in a fractional-N phase locked loop system
First Claim
1. A method for modification in a phase locked loop comprising:
- synchronizing an input to a divider in the phase locked loop to a carryout signal generated by the divider, wherein synchronizing comprises;
transmitting the carryout signal to a buffer; and
in the buffer, detecting the carryout signal and transmitting the input to the divider,wherein the input is transmitted to the divider only after the buffer detects the carryout signal.
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Accused Products
Abstract
A phase locked loop includes a buffer that synchronizes the transmission of the new count value to the completion of the previous count to avoid errors caused by dithering. The buffer is connected to a count input of the counter and transmits the new count upon receipt of the carryout signal from the counter. Alternatively, the transmission of the new value of N from the buffer is delayed after receipt by the buffer of a carryout signal from the counter. In another embodiment, a delayed version of the carryout signal is used to trigger the buffer to transmit the new count value to the counter. In another feature, a buffer synchronizes phase data to a reference signal before inputting it to a digital modulator of the phase locked loop.
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Citations
38 Claims
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1. A method for modification in a phase locked loop comprising:
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synchronizing an input to a divider in the phase locked loop to a carryout signal generated by the divider, wherein synchronizing comprises; transmitting the carryout signal to a buffer; and in the buffer, detecting the carryout signal and transmitting the input to the divider, wherein the input is transmitted to the divider only after the buffer detects the carryout signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for modification in a phase locked loop comprising:
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in a divider, generating and transmitting an output to a device; in the device, detecting the output and transmitting an input to the divider; delaying receipt of the input to the divider in the phase locked loop, the input comprising a new count value to be used by the divider. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A phase locked loop comprising:
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a phase/frequency detector, the phase/frequency having a first input and a second input, the first input being connectable to a reference signal; an oscillator for generating a desired output signal; a charge pump and a ioop filter connected in series between the output of the phase/frequency detector and an input of the oscillator; a divider connected to receive the output signal generated by the oscillator, the divider having a count input and a carryout output, the carryout output being connected to the second input of the phase/frequency detector; and a buffer connected to supply a count signal to the count input of the divider and to receive a carryout signal from the divider. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A phase locked loop comprising:
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a phase/frequency detector, the phase/frequency having a first input and a second input, the first input being connectable to a reference signal; an oscillator for generating a desired output signal; a charge pump and a loop filter connected in series between the output of the phase/frequency detector and an input of the oscillator; a divider connected to receive the output signal generated by the oscillator, the divider having a count input and a carryout output, the carryout output being connected to the second input of the phase/frequency detector and to a count source; the count source being connected to supply a count signal to the count input of the divider and to receive a carryout signal from the divider; and a delay element connected between the count source and the divider. - View Dependent Claims (29, 30, 31, 32, 33)
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34. A method for synchronizing input of phase data to a phase modulator including a phase locked loop comprising:
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temporarily storing phase data in a data synchronizer, the phase data being asynchronous with respect to a reference signal of the phase locked loop; transmitting the phase data from the data synchronizer to a modulator synchronously with respect to the reference signal, the modulator being connected to supply a new count value to a variable divider of the phase locked loop. - View Dependent Claims (35, 36)
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37. A phase locked loop comprising:
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a phase/frequency detector, the phase/frequency having a first input and a second input, the first input being connectable to a reference signal; an oscillator for generating a desired output signal; a charge pump and a loop filter connected in series between the output of the phase/frequency detector and an input of the oscillator; a divider connected to receive the output signal generated by the oscillator, the divider having a count input and a carryout output, the carryout output being connected to the second input of the phase/frequency detector and to a count source; a modulator connected to the divider; a phase data source, the phase data source being configured to generate phase data asynchronously with respect to the reference signal; and a data synchronizer having an output connected to the modulator, a first input connected to an output of the phase data source for accepting phase data, and a second input being connected to receive the reference signal, the data synchronizer being configured to transmit the phase data to the modulator synchronously with respect to the reference signal. - View Dependent Claims (38)
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Specification