Micro mirror arrays and microstructures with solderable connection sites

• US 7,203,394 B2
• Filed: 07/15/2003
• Issued: 04/10/2007
• Est. Priority Date: 07/15/2003
• Status: Expired due to Fees

• Current Assignee: Rosemount Aerospace, Inc. (Rtx Corporation)
• Original Assignee: Rosemount Aerospace, Inc. (Rtx Corporation)
• Inventors: Guo, Shuwen, Apanius, Christopher, O'Meara, Timothy R., St. Clair, Loren E., Pohl, James J., Goldman, Kenneth G., Wiegele, Thomas
• Primary Examiner(s): Pak; Sung
• Assistant Examiner(s): WONG, TINA MEI SENG
• Application Number:
  US10/620,119
• Publication Number:
  US 20050013533A1
• Time in Patent Office: 1,365 Days
• Field of Search: 385/16, 385/18
• US Class Current: 385/18
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

A micro mirror array including an upper wafer portion having a plurality of movable reflective surfaces located thereon, the upper wafer portion defining a coverage area in top view. The array further includes a lower wafer portion located generally below and coupled to the upper wafer portion. The lower wafer portion includes at least one connection site located thereon, the at least one connection site being electrically or operatively coupled to at least one component which can control the movement of at least one of the reflective surfaces. The at least one connection site is not generally located within the coverage area of the upper wafer portion.

Claims

1. A microstructure system including:

a wafer portion including a microstructure formed therein, located thereon or supported thereby wherein said wafer portion includes an upper wafer portion and a lower wafer portion located generally below and at least partially spaced apart from said upper wafer portion, and wherein said microstructure is formed in or located on said upper wafer portion, and wherein said upper wafer portion defines a coverage area in top view;

a plurality of solderable surfaces electrically or operatively coupled to said microstructure and wherein said solderable surfaces are formed or located on said lower wafer portion and are not located within said coverage area such that said solderable surfaces are not positioned under said upper wafer portion and are exposed to provide ease of access to said solderable surfaces, said solderable surfaces being arranged in a pattern; and

an electronic component having a plurality of contacts located thereon, said plurality of contacts being arranged in a pattern corresponding to said pattern of said solderable surfaces such that said electronic component is directly mechanically and electrically attachable to said solderable surfaces by a flip chip bonding process and without the use of wire bonds such that said electronic component can control, operate or receive inputs from at least part of said microstructure.

2. The microstructure system of claim 1 wherein said upper wafer portion includes an outer perimeter, and wherein said outer perimeter defines said coverage area.

3. The microstructure system of claim 1 wherein said lower wafer portion has a coverage area in top view and wherein said coverage area of said upper wafer portion is entirely contained within said coverage area of said lower wafer portion.

4. The microstructure system of claim 1 wherein said upper and lower wafer portions are directly coupled together.

5. The microstructure system of claim 4 wherein said upper wafer and lower wafer portions are coupled together by a photopatternable adhesive.

6. The microstructure system of claim 5 wherein said photopattemable adhesive is benzocyclobutene.

7. The microstructure system of claim 4 wherein said upper wafer and lower wafer portions are coupled together by a relatively low reflow temperature adhesive, said adhesive having a reflow temperature of less than about 125°

C.

8. The microstructure system of claim 1 wherein said solderable surfaces are a flip chip connection site configured to receive a chip thereon by flip chip bonding.

9. The microstructure system of claim 1 wherein each solderable surface includes a conductive pad, each pad being electrically isolated from any adjacent pad and having a melting point of less than about 250°

C.

10. The microstructure system of claim 1 wherein said electronic component is a chip and wherein said chip is coupled to said solderable surfaces by flip chip bonding.

11. The microstructure system of claim 1 further including an external controller coupled to said electronic component to control the input to or output from said electronic component to thereby control or monitor the input to or output from said microstructure.

12. The microstructure system of claim 1 wherein said microstructure is at least one of a sensor or an actuator.

13. The microstructure system of claim 1 wherein said microstructure is a mirror array including a plurality of movable reflective surfaces.

14. The microstructure system of claim 13 further including at least one component which can control the movement of at least one of said reflective surfaces, wherein said solderable surfaces are electrically or operatively coupled to said at least one component.

15. The microstructure system of claim 14 wherein said component is an electrode for controlling the movement of said at least one movable reflective surface when a voltage or current is applied across said electrode.

16. The microstructure system of claim 15 wherein at least two electrodes are located below each of said reflective surfaces such that a voltage can be applied across said electrodes to cause the associated reflective surface to move in at least two generally opposite directions.

17. The microstructure system of claim 13 wherein each reflective surface is individually movable relative to any adjacent reflective surfaces and is individually controllable.

18. The microstructure system claim 13 wherein said solderable surfaces can carry a sufficient bandwidth to allow an external controller coupled to said solderable surfaces and to said electronic component to cause and control the individual movement of each reflective surface relative to any adjacent reflective surfaces.

19. The microstructure system of claim 1 wherein said coverage area of said upper wafer portion is smaller than the coverage area of said lower wafer portion.

20. The microstructure system of claim 13 wherein said upper wafer portion includes a silicon layer, and wherein said reflective surfaces are non-silicon material located on said silicon layer.

21. The microstructure system of claim 13 wherein said upper wafer portion includes a base portion and a plurality of movable portions rotatably coupled to base portion, and wherein each reflective surface is located on one of said movable portions.

22. The microstructure system of claim 1 wherein said upper wafer portion includes at least a portion of at least one silicon-on-insulator wafer.

23. The micro structure system of claim 1 wherein said lower wafer portion is or includes at least part of a semiconductor wafer, or a ceramic substrate, or a glass substrate, or a printed circuit board.

24. The microstructure system of claim 1 wherein said lower wafer portion includes an upper surface facing said upper wafer portion, and wherein said solderable surface is located on said upper surface.

25. The microstructure system of claim 1 wherein said upper wafer portion and said lower wafer portion are coupled together by an electrically insulating material such that said upper and lower wafer portions are not directly electrically connected.

26. The microstructure system of claim 1 wherein said electronic component is not located within said coverage area such that said electronic component is not positioned under said upper wafer portion to provide ease of mounting said electronic component.

27. The microstructure system of claim 1 wherein the entirety of said solderable surface is not located within said coverage area and is not positioned under said upper wafer.

28. The system of claim 1 wherein said wafer portion includes an exposed area that is outside said coverage area, and wherein electronic component is located generally entirely in said exposed area.

29. The system of claim 1 wherein said upper wafer portion is directly coupled to said lower wafer portion, and said electronics component is directly coupled to said lower wafer portion.

30. The system of claim 1 wherein said microstructure does not include any active electronics positioned directly below said upper wafer portion that can control, operate, or receive inputs from said microstructure.

31. The system of claim 1 wherein said upper wafer portion is directly coupled to said lower wafer portion, and said electronic component is directly attached to said lower wafer portion, and wherein said electronic component is generally not positioned directly under said upper wafer portion.

32. A microstructure system including:

an upper wafer portion including a microstructure formed therein, located thereon or supported thereby, said upper wafer portion defining a coverage area in top view;

a lower wafer portion located generally below and at least partially spaced apart from said upper wafer portion, said lower wafer portion including at least one electrode for controlling the movement of at least part of said microstructure;

a solderable surface formed or located on said lower wafer portion, wherein said solderable surface is not located within said coverage area such that said solderable surface is not positioned under said upper wafer portion to provide ease of access to said solderable surface; and

an electronic component coupled to said solderable surface by flip chip bonding without wire bonds and being electrically or operatively coupled to said electrode such that said electronic component can control or operate said electrode to thereby control or operate said microstructure.

33. The microstructure system of claim 32 wherein said upper wafer portion and said lower wafer portion are coupled together by an electrically insulating material such that said upper and lower wafer portions are not directly electrically connected.

34. The microstructure system of claim 32 wherein said lower wafer portion includes an upper surface facing said upper wafer portion, and wherein said solderable surface is located on said upper surface.

35. The microstructure of claim 32 wherein said electronic component is positioned between said lower wafer portion and said upper wafer portion.

36. The microstructure system of claim 32 wherein said electronic component is a separate component that is spaced apart from said electrode.

37. A microstructure system including:

a wafer portion including a microstructure formed therein, located thereon or supported thereby wherein said wafer portion includes an upper wafer portion and a lower wafer portion located generally below and at least partially spaced apart from said upper wafer portion, and wherein said microstructure is formed in or located on said upper wafer portion, and wherein said upper wafer portion defines a coverage area in top view and an exposed area that is outside said coverage area; and

a solderable surface configured to receive an electronic component thereon in a flip chip attachment process and without wire bonds, said solderable surface being formed on, located on, or supported by said wafer portion, said solderable surface being electrically or operatively coupled to said microstructure such that an electronic component coupled to solderable surface can control, operate or receive inputs from at least part of said microstructure and wherein said solderable surface is formed or located on said lower wafer portion and is located within said exposed area, wherein said upper wafer portion and said lower wafer portion are coupled together by an electrically insulating material such that said upper and lower wafer portions are not directly electrically connected.

38. The system of claim 37 wherein said upper wafer portion and said lower wafer portion are generally electrically insulated such that a current cannot be directly passed between said upper and lower wafer portions.

39. The microstructure system of claim 37 wherein said solderable surface includes a plurality of conductive pads arranged in a pattern configured to match a pattern of conductive contacts of an electronic component.