Method and apparatus for minimizing baseband offset error in a receiver

• US 7,203,476 B2
• Filed: 01/09/2004
• Issued: 04/10/2007
• Est. Priority Date: 01/09/2004
• Status: Active Grant

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Ruelke, Charles R., Young, Richard S.
• Primary Examiner(s): Urban; Edward
• Assistant Examiner(s): Le; Nhan T.
• Application Number:
  US10/754,654
• Publication Number:
  US 20050153676A1
• Time in Patent Office: 1,187 Days
• Field of Search: 375/345, 455/232.1, 455/240.1, 455/250.1, 455/324, 455/234.1, 455/296, 455/266, 455/230, 455/313, 455/323, 455/334, 455/338, 455/339, 455255-260
• US Class Current: 455/324
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

An adaptive dc compensation technique (100) eliminates dc error for both digital and constant envelope modulation protocols (108). For analog modulation, a dc averaging technique utilizes piece-wise continuous dc averaging (110) that calculates discrete dc error values over a variable number of samples (112) and updates the dc compensation value as a fixed value for a specified sample length (114). The piece-wise “update-and-hold” technique (110) results in a pseudo high pass filter response with an equivalent corner. For digital modulation, a continuous high pass filter section of the receiver is enabled (120).

Claims

1. A dc averaging technique for a direct conversion receiver, comprising the steps of:

receiving a radio frequency (RF) signal;

converting the received RF signal to a baseband signal, the baseband signal being subject to dc offset caused by a plurality of dc error sources;

calculating discrete dc error values independent of the plurality of dc error sources, over a variable number of samples using piece-wise continuous dc averaging to generate a dc compensation value;

updating the dc compensation value as a fixed value for each sample to approximate a high pass filter response with an equivalent corner;

applying the updated dc compensation value to the baseband signal;

wherein the step of updating the dc compensation value includes adjusting an alpha factor, used in the discrete error calculation, based on an allowable integration period and targeted accuracy.

2. The dc averaging technique of claim 1, wherein the step of updating the dc compensation value occurs over a predetermined step size and update rate.

3. The dc averaging technique of claim 2, wherein the step size is adapted based on at least one of:

operating protocol, on-channel RF operating environment, possible off-channel dynamic interferers, and variations in power of the received RF signal power.

4. The dc averaging technique of claim 1, wherein the integration period is adapted depending on both operating protocol and the rate of change in the received RF signal power.

5. A method of compensating dc offset error in a direct conversion receiver, comprising:

receiving a Radio Frequency (RF) signal;

converting the RF signal to a baseband signal;

sampling the baseband signal over a sampling period of variable sample lengths;

determining whether the received RF signal incorporates analog or digital modulation;

for received RF signals incorporating analog modulation, implementing piece-wise continuous averaging comprised of;

calculating discrete dc error values for each sample period;

updating a dc compensation value as a fixed value for each sample period based on the discrete dc error values for each period;

holding the dc compensation value for a particular sample period constant for that sample period; and

for received RF signals incorporating digital modulation, disabling the piece-wise continuous averaging; and

enabling a continuous high pass filter section of the receiver with corner sufficiently low to eliminate baseband dc errors response for digital protocols.

6. An apparatus for compensating dc offset in a direct conversion receiver, including:

means for converting an RF signal to a baseband signal, the baseband signal being subject to dc offset caused by a plurality of dc error sources;

an amplifier for amplifying the baseband signal and providing an amplified signal;

a low pass filter for filtering the amplified signal to provide a filtered signal;

an analog-to-digital converter for converting the filtered signal to a digital signal;

an integrator for sampling the digital signal over a sample period of variable lengths and calculating a discrete integrated dc error value for the sample period, regardless of the dc error source;

a controller for receiving the calculated dc error value and updating and holding an updated dc compensation value as a fixed value for each period based on the discrete error value for each period;

a digital signal processor for triggering the controller to update the dc compensation value; and

a digital-to-analog converter for converting the updated dc compensation value to an analog signal to be applied to the baseband signal.

7. A method for minimizing baseband offset error in a receiver, including the step of:

receiving a radio frequency (RF) signal;

converting the RF signal to a baseband signal;

determining a modulation protocol of the received RF signal as being one of;

digital modulation and analog modulation;

initiating a dc compensation value based on the modulation protocol;

for the analog modulation protocol;

holding the dc compensation value constant while initiating continuous piece-wise dc error correction to reduce error in the baseband signal; and

for the digital modulation protocol;

enabling a hardware dc offset correction in response to a second set of signal conditions to reduce error in the baseband signal.

8. The receiver of claim 7, wherein the step of enabling a hardware dc offset correction comprises the step of enabling a continuous high pass filter section of the receiver.

9. The receiver of claim 7, wherein the step of initiating continuous piece-wise dc error correction results in an approximation of a high pass filter response with equivalent corner.

10. A method of compensating dc offset error in a direct conversion receiver, comprising:

receiving a radio frequency (RF) signal having an operating protocol;

measuring an initial dc hardware offset error;

performing an initial hardware dc offset correction using preset default DSP parameters;

alpha, integration period, update rate, and step size (a, Tp, Tu, and S respectively);

determining whether the operating protocol is analog or digital;

scaling the dc offset based on the operating protocol;

resetting the DSP parameters based on the operating protocol;

initiating I/Q integration to determine dc offset error;

calculating an I/Q dc compensation value based on the determined dc offset error;

comparing the calculated I/Q dc compensation value to a maximum dc update step size provided by the reset DSP parameter, S;

updating the dc compensation value based on the step of comparing;

remeasuring the hardware dc offset error;

comparing the remeasured hardware dc offset error to predetermined limits;

determining signal strength conditions, if the dc offset error does not exceed the predetermined limits;

under weak signal conditions, returning to the step of initiating the I/Q integration; and

under strong signal conditions, resetting the DSP parameters and adjusting the integration factor, a, prior to returning to the step of integration;

determining a cause for the hardware dc offset error, if the dc offset error does exceed the predetermined limits;

executing a hardware dc offset correction based on the cause of the hardware dc offset error;

returning to the step of determining whether the operating protocol is analog or digital when the cause of the hardware dc offset error is due to a channel or scan change; and

resetting the DSP parameters, adjusting the integration factor and returning to the step of initiating I/Q integration, when the cause of the hardware dc offset error is not due to channel or scan change.

11. The method of claim 10, wherein the step of initiating I/Q integration to determine dc offset error utilizes the following:

Idc(n)=a*Idc(n−

1)+(1−

a)*I(n)

Qdc(n)=a*Qdc(n−

1)+(1−

a)*Q(n), for n=1 to Tp.