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Error detection, documentation, and correction in a flash memory device

  • US 7,203,874 B2
  • Filed: 05/08/2003
  • Issued: 04/10/2007
  • Est. Priority Date: 05/08/2003
  • Status: Active Grant
First Claim
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1. A flash memory device comprising:

  • a controller circuit for generating memory control signals;

    a primary memory array coupled to the controller circuit, the primary memory array comprising a plurality of non-volatile memory cells; and

    an error documentation memory array of non-volatile memory cells, coupled to the controller circuit, that stores documentation data regarding a first over-programmed memory cell in the primary memory array, the documentation data comprising a data offset indicating a quantity of states between a desired data and an actual programmed data of the first over-programmed memory cell.

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