Error detection, documentation, and correction in a flash memory device

• US 7,203,874 B2
• Filed: 05/08/2003
• Issued: 04/10/2007
• Est. Priority Date: 05/08/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US10/431,889
• Publication Number:
  US 20040243909A1
• Time in Patent Office: 1,433 Days
• Field of Search: 714/718, 714/719, 714/723, 365/201, 711/103
• US Class Current: 714/723
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3463 Circuits or methods to detect overprogrammed nonvolatile memory cells, usually during program verification
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as well, deleting the documentation data relating to the over-programmed bits.

Claims

1. A flash memory device comprising:

a controller circuit for generating memory control signals;

a primary memory array coupled to the controller circuit, the primary memory array comprising a plurality of non-volatile memory cells; and

an error documentation memory array of non-volatile memory cells, coupled to the controller circuit, that stores documentation data regarding a first over-programmed memory cell in the primary memory array, the documentation data comprising a data offset indicating a quantity of states between a desired data and an actual programmed data of the first over-programmed memory cell.

2. The device of claim 1 wherein the documentation data comprises a location of I/O data to have been stored in the first over-programmed memory cell.

3. The device of claim 1 wherein the device is a NAND-type flash memory device.

4. The device of claim 1 wherein the device is a NOR-type flash memory device.

5. The device of claim 1 wherein the controller circuit is adapted to compare memory address signals input to the device to determine a first memory address signal indicating the first over-programmed memory cell.

6. The device of claim 1 wherein the controller circuit is adapted to execute an erase method comprising:

erasing at least a portion of a first array block of the primary memory array, the first array block comprising the first over-programmed memory cell; and

erasing the error documentation memory array such that the documentation data is erased.

7. A flash memory device comprising:

a primary memory array comprising a plurality of non-volatile memory cells;

an error documentation memory array of non-volatile memory cells that stores documentation data regarding a first over-programmed memory cell in the primary memory array, the documentation data comprising a data offset indicating a quantity of states between a desired data and an actual programmed data of the first over-programmed memory cell; and

a controller circuit for generating memory control signals and adapted to execute an error detection, documentation, and correction method comprising;

detecting the first over-programmed memory cell;

programming the first over-programmed memory cell to a subsequent state; and

storing, in the error documentation memory array, first documentation data regarding first over-programmed memory cell.

8. The device of claim 7 wherein the first documentation data comprises an address for the first over-programmed memory cell.

9. The device of claim 7 wherein the controller circuit further comprises a comparison circuit that compares memory addresses input to the device such that a first memory address associated with the first over-programmed memory cell is flagged.

10. The device of claim 9 wherein the controller circuit is further adapted to execute a read operation comprising:

comparing input memory addresses, input to the device, with the first memory address;

when the first memory address is input, reading the first documentation data; and

reading I/O data in response to the first documentation data.

11. An electronic system comprising:

a processor that controls operation of the electronic system; and

a flash memory device, coupled to the processor, comprising;

a controller circuit for generating memory control signals;

a primary memory array coupled to the controller circuit, the primary memory array comprising a plurality of non-volatile memory cells; and

an error documentation memory array of non-volatile memory cells, coupled to the controller circuit, that stores documentation data regarding a first over-programmed memory cell in the primary memory array, the documentation data comprising a data offset indicating a quantity of states between a desired data and an actual programmed data of the first over-programmed memory cell.