Retiming circuits using a cut-based approach
First Claim
1. A method for retiming an integrated circuit in an electronic design automation (EDA) environment, comprising:
- performing a timing analysis for one or more paths in the integrated circuit to obtain delay times for a signal propagating along the paths;
selecting a path based on the delay times obtained, the path selected having a delay time that fails a timing constraint, the path selected originating at a source sequential element and ending at a destination sequential element, the path selected further comprising two or more logic instances;
determining a retiming location along the path selected where one of the source sequential element or the destination sequential element can be repositioned in order to satisfy the timing constraint, the retiming location being at least two logic instances from the one of the source sequential element or the destination sequential element;
updating a design database of the integrated circuit to reposition the one of the source sequential element or the destination sequential element to the retiming location; and
storing the updated design database.
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Accused Products
Abstract
Methods and apparatus for retiming an integrated circuit are described. According to certain embodiments, the retiming comprises performing a timing analysis for one or more paths in the integrated circuit to obtain slack values, selecting one of the paths based on the slack values obtained, and determining a retimeable cut along the path selected. The retimeable cut in these exemplary embodiments comprises a set of input pins for one or more logic instances in the integrated circuit to which one or more retimed sequential elements can be coupled in order to improve the slack value of the path selected. In particular embodiments, the retimeable cut is automatically selected from multiple possible cuts along the path selected. Other embodiments for retiming integrated circuits are disclosed, as well as integrated circuits and circuit design databases retimed by the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.
53 Citations
46 Claims
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1. A method for retiming an integrated circuit in an electronic design automation (EDA) environment, comprising:
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performing a timing analysis for one or more paths in the integrated circuit to obtain delay times for a signal propagating along the paths; selecting a path based on the delay times obtained, the path selected having a delay time that fails a timing constraint, the path selected originating at a source sequential element and ending at a destination sequential element, the path selected further comprising two or more logic instances; determining a retiming location along the path selected where one of the source sequential element or the destination sequential element can be repositioned in order to satisfy the timing constraint, the retiming location being at least two logic instances from the one of the source sequential element or the destination sequential element; updating a design database of the integrated circuit to reposition the one of the source sequential element or the destination sequential element to the retiming location; and
storing the updated design database. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for retiming an integrated circuit in an electronic design automation (EDA) environment, comprising:
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identifying a failing signal path in the integrated circuit, the failing signal path originating at a source sequential element, extending through one or more logic instances of a logic cone, and ending at a destination sequential element, the failing signal path having a delay time that fails to meet a timing constraint; selecting a location along the failing signal path where one of the source sequential element or the destination sequential element can be repositioned to improve the delay time of the failing signal path, the location selected being coupled to an input of a related one of the logic instances; from the location selected, searching output paths and input paths of the related logic instance to identify one or more additional sequential elements to reposition in order to retain circuit functionality, the act of searching the output paths and the input paths comprising identifying one or more additional locations in the integrated circuit for repositioning the one or more additional sequential elements in order to retain circuit functionality; and storing the location selected and one or more additional locations identified. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method for identifying a retimeable cut in an integrated circuit design comprising:
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selecting a signal path to be retimed, the signal path originating at a source sequential element, extending through one or more logic instances, and ending at a destination sequential element; finding a retimeable cut along the signal path, the retimeable cut including an indication of a location across one or more of the logic instances where one of the source sequential element or the destination sequential element can be relocated, the act of finding the retimeable cut comprising, performing a forward trace from one or more output pins of a selected logic instance in the signal path, and performing a backward trace from one or more input pins of the selected logic instance in the signal path, and performing a timing evaluation using the retimeable cut to determine delay times associated with the retimeable cut; and
saving the retimeable cut if the delay times do not violated related timing constraints. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A method for retiming an integrated circuit in an electronic design automation (EDA) environment, comprising:
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a step for performing a timing analysis for one or more paths in the integrated circuit to obtain slack values; a step for selecting one of the paths based on the slack values obtained; a step for determining a retimeable cut along the path selected, the retimeable cut comprising a set of input pins for one or more logic instances in the integrated circuit to which one or more retimed sequential elements can be directly coupled, respectively, in order to improve the slack value of the path selected, and to which the one or more logic instances were not previously directly coupled, the retimeable cut being automatically selected from two or more possible cuts along the path selected; and a step for saving the retimable cut. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46)
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Specification