Method for planarization etch with in-situ monitoring by interferometry prior to recess etch

• US 7,204,934 B1
• Filed: 10/31/2001
• Issued: 04/17/2007
• Est. Priority Date: 10/31/2001
• Status: Expired due to Fees

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Vahedi, Vahid, Miller, Alan, Braly, Linda, Edelberg, Erik
• Primary Examiner(s): Ahmed; Shamim
• Application Number:
  US10/002,676
• Time in Patent Office: 1,994 Days
• Field of Search: 216/38, 216/59, 216/67, 216/88, 216/60, 438/9, 438/692, 438/720, 438/710
• US Class Current: 216/59
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

A method for processing recess etch operations in substrates is provided including forming a hard mask over the substrate and etching a trench in the substrate using the hard mask, and forming a dielectric layer over the hard mask and in the trench, where the dielectric layer lines the trench. A conductive material is then applied over the dielectric layer such that a blanket of the conductive material lies over the hard mask and fills the trench, and the conductive material is etched to substantially planarize the conductive material. The etching of the conductive material triggers an endpoint just before all of the conductive material is removed from over the dielectric layer that overlies the bard mask. The conductive material is recess etched to remove the conductive material over the dielectric layer that overlies the hard mask and removes at least part of the conductive material from within the trench.

Claims

1. A method for processing recess etch operations in substrates, comprising:

a) forming a hard mask over the substrate;

b) etching a trench in the substrate using the hard mask;

c) forming a dielectric layer over the hard mask and in the trench, the electric layer configured to line the trench;

d) applying a conductive material over the dielectric layer such that a blanket of the conductive material lies over the hard mask and fills the trench;

e1) planarization etching the conductive material to substantially planarize the conductive material;

e2) utilizing interferometric endpoint detection to identify an endpoint of the planarization etching, the endpoint of the planarization etching occurring so as to leave a portion of the conductive material over the dielectric layer that overlies the hard mask;

e3) stopping the planarization etching upon identification of the endpoint of the planarization etching; and

f) recess etching the conductive material so as to remove the conductive material over the dielectric layer that overlies the hard mask and removes at least part of the conductive material from within the trench, wherein the recess etching is performed using a different chemistry than that used to perform the planarization etching.

2. A method for processing recess etch operations in substrates as recited in claim 1, further comprising:

repeating operations (c) through (f) one or more times to form multiple layers of the conductive material in the trench.

3. A method for processing recess etch operations in substrates as recited in claim 1, wherein the hardmask is protected by utilizing the interferometric endpoint detection to identify an endpoint of the planarization etching.

4. A method for processing recess etch operations in substrates as recited in claim 1, wherein the planarization etching and the recess etching occurs in an etch chamber thereby increasing wafer production throughput.

5. A method for processing recess etch operations in substrates as recited in claim 1, wherein the planarization etching of the conductive material utilizes a first chemistry including Cl₂, He, and SF₆.

7. A method for processing recess etch operations in substrates as recited in claim 1, wherein the recess etching utilizes a second chemistry including Ar and SF₆.

8. A method for processing recess etch operations in substrates as recited in claim 7, wherein an Ar flow rate is between about 0 sccms and about 300 sccms, and a SF₆ flow rate is between about 10 sccms and about 100 sccms.

9. A method for processing recess etch operations in substrates as recited in claim 1, wherein the recess etching is used with one of an interferometric endpoint (IEP) detection and a timed etching to monitor the removal of the conductive material.

6. A method for processing recess etch operations in substrates as recited in claim 6, wherein a Cl₂ flow rate is between about 20 sccms and about 200 sccms, a He flow rate is between about 20 sccms and about 500 sccms, and a SF₆ flow rate is between about 2 sccms and about 50 sccms.

10. A method for processing recess etch operations, in substrates, comprising:

a) forming a hard mask over the substrate;

b) etching a trench in the substrate using the hard mask;

c) forming a dielectric layer over the hard mask and in the trench, the dielectric layer configured to line the trench;

d) applying a conductive material over the dielectric layer such that a blanket of the conductive material lies over the hard mask and fills the trench;

e1) planarization etching the conductive material using a first chemistry to substantially planarize the conductive material;

e2) utilizing interferometric endpoint detection to identify an endpoint of the planarization etching, the endpoint of the planarization etching occurring so as to leave a portion of the conductive material over the dielectric layer that overlies the hard mask;

e3) stopping the planarization etching upon identification of the endpoint of the planarization etching;

f) recess etching the conductive material using a second chemistry and one of the interferometry monitoring and a timed etch so as to remove the conductive material over the dielectric layer that overlies the hard mask and removes at least part of the conductive material from within the trench; and

g) repeating operations (c) through (f) one or more times to form multiple layers of the conductive material in the trench.

11. A method for processing recess etch operations in substrates as recited in claim 10, wherein the hardmask is protected by utilizing the interferometric endpoint detection to identify an endpoint of the planarization etching.

12. A method for processing recess etch operations in substrates as recited in claim 10, wherein the planarization etching and the recess etching occurs in an etch chamber thereby increasing wafer production throughput.

13. A method for processing recess etch operations in substrates as recited in claim 10, wherein the first chemistry including Cl₂, He, and SF₆.

14. A method for processing recess etch operations in substrates as recited in claim 13, wherein a Cl₂ flow rate is between about 20 sccms and about 200 sccms, a He flow rate is between about 20 sccms and about 500 sccms, and a SF₆ flow rate is between about 2 sccms and about 50 sccms.

15. A method for processing recess etch operations in substrates as recited in claim 10, wherein the second chemistry including Ar and SF₆.

16. A method for processing recess etch operations in substrates as recited in claim 15, wherein an Ar flow rate is between about 0 sccms and about 300 sccms, and a SF₆ flow rate is between about 10 sccms and about 100 sccms.

17. A method for processing recess etch operations in substrates, comprising:

a) forming a hard mask over the substrate;

b) etching a trench in the substrate using the hard mask;

c) forming a silicon dioxide layer over the hard mask and in the trench, the silicon dioxide layer configured to line the trench;

d) applying a polysilicon material over the dielectric layer such that a blanket of the polysilicon material lies over the hard mask and fills the trench;

e1) planarization etching the polysilicon material to substantially planarize the polysilicon material, the planarization etching of the polysilicon material using a first chemistry including Cl₂, He, and SF₆;

e2) utilizing interferometric endpoint detection to identify an endpoint of the planarization etching, the endpoint of the planarization etching occurring so as to leave a portion of the polysilicon material over the silicon dioxide layer that overlies the hard mask;

e3) stopping the planarization etching upon identification of the endpoint of the planarization etching; and

f) recess etching the polysilicon material using one of the interferometry monitoring and a timed etch so as to remove the polysilicon material over the silicon dioxide layer that overlies the hard mask and removes at least part of the polysilicon material from within the trench, the recess etching using a second chemistry including Ar and SF₆.

18. A method for processing recess etch operations in substrates as recited in claim 17, wherein the first chemistry is defined by a Cl₂ flow rate of about 100 sccms, a He flow rate of about 100 sccms, and a SF₆ flow rate of about 10 sccms.

19. A method for processing recess etch operations in substrates as recited in claim 17, wherein the second chemistry is defined by an Ar flow rate of about 200 sccms and a SF₆ flow rate of about 15 sccms.

20. A method for processing recess etch operations in substrates as recited in claim 17, wherein the planarization etching occurs in an etching chamber which utilizes a top power between 800 watts to about 1200 watts, a bottom power between 40 watts to about 100 watts, a gas pressure of between about 3 mTorr to about 10 mTorr, and a temperature of between about 10 C. and about 60 C.

21. A method for processing recess etch operations in substrates as recited in claim 17, wherein the planarization etching occurs in an etching chamber which utilizes a top power of about 1000 watts, a bottom power of about 66 watts, a gas pressure of about about 5 mTorr, and a temperature of about 30 C.

22. A method for processing recess etch operations in substrates as recited in claim 17, wherein the interferometric endpoint detection includes using a first light signal with a first wavelength, and a second light signal with a second wavelength, the first wavelength being different than the second wavelength.

23. A method for processing recess etch operations in substrates as recited in claim 17, further comprising:

repeating operations (c) through (f) one or more times to form multiple layers of the polysilicon material in the trench.