Method of fabricating micro-electromechanical systems

• US 7,205,173 B2
• Filed: 03/19/2003
• Issued: 04/17/2007
• Est. Priority Date: 03/20/2002
• Status: Expired due to Fees

• Current Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Original Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Inventors: Hamilton, David James, Bunyan, Robert John Tremayne, McNie, Mark Edward, Brunson, Kevin Michael
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US10/508,129
• Publication Number:
  US 20050139871A1
• Time in Patent Office: 1,490 Days
• Field of Search: 438 48- 52
• US Class Current: 438/48
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit

Abstract

A MEMS incorporating a sensing element and a JFET electrically connected to the sensing element is fabricated by the steps of: forming a first layer of electrically insulating barrier material on a surface of a substrate; patterning the first layer so as to expose a first region of the substrate; doping by ion implantation the first region of the substrate to form a well region of the JFET; forming a second layer of barrier material on the surface of both the first layer and the first region of the substrate; patterning the barrier material so as to expose a part of the first region of the substrate; doping by ion implantation the exposed part of the first region of the substrate to form source and drain contact areas of the JFET; patterning the barrier material so as to expose a second region of the substrate; and doping by ion implantation the second region of the substrate to form gate and substrate contact areas of the JFET in a single implantion step. The monolithic integration of the JFET with the MEMS enables the bond wires for interconnecting the sensing element and the associated sensing electronic circuitry to be provided only after the buffering stage of such circuitry. This means that the bond wires interconnecting the buffering stage and the remainder of the circuitry are connected to a low impedance node which is less sensitive to noise and parasitic capacitive loading. Thus greater detection accuracy can be achieved by virtue of the fact that the parasitic capacitances are reduced to a minimum.

Claims

1. A method of fabricating a micro-electromechanical system (MEMS) incorporating a sensing element and a junction field-effect transistor (JFET) electrically connected to the sensing element, the method comprising the steps of:

(a) forming a first layer of electrically insulating barrier material on a surface of a substrate;

(b) patterning the first layer so as to expose a first region of the substrate;

(c) doping by ion implantation the first region of the substrate to form a well region of the JFET;

(d) forming a second layer of barrier material on the surface of both the first layer and the first region of the substrate;

(e) patterning the second layer of barrier material so as to expose a part of the first region of the substrate;

(f) doping by ion implantation the exposed part of the first region of the substrate to form source and drain contact areas of the JFET;

(g) patterning the second layer of barrier material so as to expose a second region of the substrate; and

(h) doping by ion implantation the second region of the substrate to form gate and substrate contact areas of the JFET in a single implantation step.

2. A method according to claim 1, wherein, prior to patterning of the second layer in step (e), the thickness of the second layer on the substrate is substantially less than the combined thickness of the first and second layers where these are superimposed on the substrate, so that sufficient barrier material remains to prevent ion implantation in the second region in step (f).

3. A method according to claim 1, wherein, in a further step to reduce gate-to-substrate leakage, a spacer is formed around the edge of a well formed by coating of the first region with the second layer.

4. A method according to claim 3, wherein the spacer is formed by forming another layer of barrier material on the second layer and by directionally etching said other layer over the whole of its extent to leave the spacer in the areas where the layer is thicker due to the underlying topology.

5. A method according to claim 1, wherein, during patterning of the barrier material so as to expose said part of the first region through which the source and drain contact areas are implanted, portions of the barrier layer are etched to expose said part and simultaneously further portions of the layer overlying the second region are etched only part of the way through the thickness of the layer.

6. A method according to claim 1, wherein an annealing step is provided for activating the doping.

7. A method according to claim 1, wherein a metallisation step is provided in which one or more metallisation layers are deposited and patterned to form electrically conductive connections to the contact areas of the JFET and the sensing element.

8. A method according to claim 7, wherein a further patterning step is provided in which contact holes are formed in a further layer of barrier material for establishing electrical contact between the electrical conductive connections and the contact areas.

9. A method according to claim 1, wherein a resistor forming step is provided in which at least one biasing resistor is formed by depositing and patterning a further layer of material and doping an area exposed by patterning to form the biasing.

10. A method according to claim 9, wherein the further layer of material is a polysilicon layer.

11. A method according to claim 1, wherein a biasing diode junction for biasing the JFET is formed by the fabrication steps.

12. A method according to claim 1, wherein each patterning step involves a lithographic process in which the layer is selectively exposed through a photoresist mask and the layer is selectively etched.

13. A method according to claim 1, wherein an epitaxial layer is formed at least in selected regions on the surface of the substrate.

14. A method according to claim 1, wherein a mechanical actuator of the MEMS is formed by deep reactive ion etching (DRIE), by anisotropic wet etching or by sacrificial surface micromachining.