Method of fabricating mobility enhanced CMOS devices

• US 7,205,206 B2
• Filed: 03/03/2004
• Issued: 04/17/2007
• Est. Priority Date: 03/03/2004
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Belyansky, Michael P., Gluschenkov, Oleg
• Primary Examiner(s): Huynh; Andy
• Application Number:
  US10/708,430
• Publication Number:
  US 20050194699A1
• Time in Patent Office: 1,140 Days
• Field of Search: 438/199, 438/424, 438/426, 438/427, 438/435, 257/21.546, 257/21.547
• US Class Current: 438/424
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

Claims

1. A method of forming a semiconductor structure comprising steps of:

forming spacer voids between a gate a mandrel layer;

creating recesses in a substrate below and in alignment with the spacer voids;

filling a first portion of the recesses with a stress imposing material;

filling a second portion of the recesses with a semiconductor material; and

removing the mandrel layer.

2. A method according to claim 1, further including forming dummy spacers between the mandrel layer and the gate and forming a nitride interface as an etch stop in the recesses.

3. A method according to claim 1, wherein the recesses include a first recess and a second recess, the first recess and the second recess having a depth greater than a depth of the bottom of a channel area of the gate.

4. A method according to claim 3, wherein the first recess has a depth substantially equal to a depth of the second recess.

5. A method according to claim 3, wherein the first recess has a depth of about 500 to 2000 angstroms.

6. A method according to claim 1, further comprising forming dummy spacers and removing the dummy spacers to form the spacer voids, wherein:

a first dummy spacer has a first width;

a second dummy spacer has a second width;

a first recess of the recesses has a width substantially equal to the first width of the first dummy spacer; and

a second recess of the recesses has a width substantially equal to the second width of the second dummy spacer.

7. A method according to claim 6, wherein the first width is substantially equal to the second width.

8. A method according to claim 7, wherein the first width is about 100 to 1000 Å

.

9. A method according to claim 1, wherein the recesses are substantially equidistant from the gate.

10. A method according to claim 1, wherein the stress imposing material is a material that introduces a compressive stress.

11. A method according to claim 1, wherein the stress imposing material is a material that introduces a tensile stress.

12. A method according to claim 1, wherein the stress imposing material is a material that introduces a stress that degrades electron or hole mobility in the semiconductor structure.

13. A method according to claim 1, wherein the stress imposing material is a material that introduces a stress that enhances electron or hole mobility in the semiconductor structure.

14. A method according to claim 1, wherein the stress imposing material is a material comprised of at least one of polysilicon, SiO₂, Si_1-xGe_x, Si_xN_y, or Si_xON_y.

15. A method according to claim 1, wherein the semiconductor material is comprised of epitaxially grown Si.

16. A method according to claim 1, wherein:

the gate is an n-channel field effect transistor gate; and

the stress imposing material is a material that introduces a tensile stress in a direction parallel to a direction of current flow for the n-channel field effect transistor gate.

17. A method according to claim 1, wherein:

the gate is a p-channel field effect transistor gate; and

the stress imposing material is a material that introduces a compressive stress in a direction parallel to a direction of current flow for the p-channel field effect transistor gate.

18. A method according to claim 1, further comprising a step of annealing after filling the first portion of the recesses with the stress imposing material.

19. A method of forming a semiconductor structure comprising steps of:

forming dummy spacers on sides of a gate formed on a substrate;

forming a mandrel layer with portions of the mandrel layer abutting the dummy spacers;

removing the dummy spacers to form spacer voids between the gate and the mandrel layer;

creating recesses in the substrate below and in alignment with the spacer voids

filling a first portion of the recesses with a stress imposing material; and

filling a second portion of the recesses with a semiconductor material.

20. A method according to claim 19, further comprising the step of:

removing the mandrel layer,

wherein;

the first portion of the recesses is below the bottom of a channel area of the gate; and

the stress imposing material is a material that introduces one of a compressive stress and a tensile stress in the channel area.

21. A method according to claim 20, wherein the gate is one of:

an n-channel field effect transistor gate and the stress imposing material is a material that introduces a tensile stress in a direction parallel to a direction of current flow for the n-channel field effect transistor gate; and

a p-channel field effect transistor gate and the stress imposing material is a material that introduces a compressive stress in a direction parallel to a direction of current flow for the p-channel field effect transistor gate.

22. A method according to claim 19, wherein the stress imposing material is a material comprised of at least one of polysilicon, SiO₂, Si_1-xGe_x, Si_xN_y, or Si_xON_y.

23. A method of forming a semiconductor structure comprising steps of:

forming a field effect transistor gate on a substrate;

forming a first dummy spacer and a second dummy spacer on sides of the field effect transistor gate;

forming a mandrel layer with portions of the mandrel layer abutting the first and second dummy spacers for the field effect transistor gate;

after masking the semiconductor structure, introducing stress to the field effect transistor gate; and

removing the mandrel layer,

wherein the step of introducing stress material comprises;

removing the first and second dummy spacers from the field effect transistor gate to form first and second spacer voids between the field effect transistor gate and the portions of the mandrel layer;

creating a first recess in the substrate below and in alignment with the first spacer void and a second recess in the substrate below and in alignment with the second spacer void for the field effect transistor gate;

filling a first portion of the first recess and a first portion of the second recess with a stress imposing material configured to enhance performance of the field effect transistor gate;

filling a second portion of the first recess and a second portion of the second recess for the field effect transistor gate with a semiconductor material; and

unmasking the semiconductor structure.

24. A method according to claim 23, wherein the steps are performed in the order recited.

25. A method according to claim 23, wherein one of:

the field effect transistor gate is an n-channel field effect transistor gate and the stress imposing material configured to enhance performance of the n-channel field effect transistor gate is a material that introduces a tensile stress in a direction parallel to a direction of current flow for the n-channel field effect transistor gate; and

the field effect transistor gate is a p-channel field effect transistor gate and the stress imposing material configured to enhance performance of the p-channel field effect transistor gate is a material that introduces a compressive stress in a direction parallel to a direction of current flow for the n-channel field effect transistor gate.

26. A method according to claim 23, wherein the stress imposing material is a material that introduces a compressive stress.

27. A method according to claim 23, wherein the stress imposing material is a material that introduces a tensile stress.

28. A method according to claim 23, wherein the stress imposing material is a material that introduces a stress that degrades electron or hole mobility in the semiconductor structure.

29. A method according to claim 23, wherein the stress imposing material is a material that introduces a stress that enhances electron or hole mobility in the semiconductor structure.

30. A method according to claim 23, wherein the stress imposing material is a material comprised of at least one of polysilicon, SiO₂, Si_1-xGe_x, Si_xN_y, or Si_xON_y.

31. A method according to claim 23, wherein the semiconductor material is comprised of epitaxially grown Si.

32. A method of providing compressive or tensile imposing materials selectively beneath and in alignment with spacer areas of a semiconductor substrate and adjacent to channel areas to enhance electron and hole mobility in CMOS circuits, comprising:

forming disposable dummy spacers on the semiconductor substrate and adjacent to the channel areas of a patterned gate;

forming a mandrel over active device regions of the patterned gate, abutting the disposable dummy spacers;

after forming of the mandrel, removing the disposable dummy spacers to form spacer voids;

etching recesses into the semiconductor substrate at a bottom of the spacer voids;

introducing a compressive or tensile imposing material into a portion of the recesses; and

filling a remainder of the recesses with material.

33. The method of claim 32, wherein the compressive or tensile imposing material fill the recesses up to about a surface of the semiconductor substrate.

34. The method of claim 33, wherein:

the compressive imposing material undergoes a volume expansion to impart compressive stresses; and

the tensile imposing material undergoes a volume contraction to impart tensile stresses.

35. The method of claim 32, wherein a depth of the recesses are approximately 500 to 2000 Angstroms.

36. The method of claim 32, wherein the recesses are partially filled with the compressive or tensile imposing material.

37. The method of claim 32, wherein the disposable dummy spacers are comprised of a nitride.

38. The method of claim 32, wherein the disposable dummy spacers are comprised of a SiO₂ liner and a polysilicon film.

39. The method of claim 32, wherein the mandrel is comprised of a dielectric film or a self-planarizing material that withstands etching of the disposable dummy spacers.

40. The method of claim 32, further comprising forming a nitride interface in the recesses.

41. The method of claim 32, wherein:

the tensile imposing material is a dielectric film or polysilicon which is annealed by rapid thermal annealing (RTA) between 950 to 1050°

C. such that polysilicon grains grow and experience a volume contraction to create a tensile stress; and

the compressive imposing material is a dielectric film, Si<sub>1−

x</sub>Ge_x or SiO₂.