High performance strained CMOS devices

• US 7,205,207 B2
• Filed: 02/18/2005
• Issued: 04/17/2007
• Est. Priority Date: 10/16/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Gluschenkov, Oleg G.
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): Isaac; Stanetta
• Application Number:
  US11/060,784
• Publication Number:
  US 20050148146A1
• Time in Patent Office: 788 Days
• Field of Search: 438/221, 438/424, 438/426, 257/E21.549
• US Class Current: 438/424
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO₂ interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si—SiO₂ interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.

Claims

1. A process of forming a semiconductor structure, comprising:

forming a structure comprised of a silicon layer, a silicon dioxide layer on the silicon layer, and a silicon nitride layer on the silicon dioxide layer; and

forming a shallow trench isolation on the structure based on a determined distance between the shallow trench isolation and an active device, the shallow trench isolation formed to have a first shallow trench isolation side having at least one overhang, in a first direction, selectively configured to prevent bird'"'"'s beak formations where compressive stresses by the bird'"'"'s beak formations would degrade device performance based on the determined distance, and a second shallow trench isolation side being transverse to the first shallow trench side and being devoid of an overhang when the determined distance prevents the bird'"'"'s beak formations.

2. The process of claim 1, wherein the step of forming the shallow trench isolation includes:

etching a portion of the silicon nitride layer, the silicon dioxide layer and the silicon layer to form a trench;

etching sidewall portions of the silicon nitride layer in the trench creating a recession of the silicon nitride layer relative to the trench for the first shallow trench isolation side; and

depositing silicon dioxide into the trench and recession to form the shallow trench isolation with a first shallow trench isolation side having an overhang.

3. The process of claim 2, further comprising a step of forming a field effect transistor having a source, a drain, a gate, and a direction of current flow from the source to the drain.

4. The process of claim 3, wherein the distance from the gate of the field effect transistor to the first shallow trench isolation side is less than or equal to a distance within which oxidation induced stress adjacent to the first shallow trench isolation side would affect performance of the field effect transistor.

5. A process of forming a pFET structure, comprising:

forming a structure comprised of a silicon layer, a silicon dioxide layer on the silicon layer, and a silicon nitride layer on the silicon dioxide layer; and

forming a shallow trench isolation having a first shallow trench isolation side with an overhang over a portion of the silicon layer and the silicon dioxide layer in a transverse direction, based on a distance between an active device and the shallow trench isolation, to prevent a bird'"'"'s beak formation, and a second shallow trench isolation side being devoid of an overhang in a direction parallel to a direction of current flow.

6. The process of claim 5, further comprising removing the silicon nitride layer using hot phosphoric acid, after the formation of the shallow trench isolation.

7. A method of forming a device, comprising:

forming a silicon dioxide layer over a silicon layer;

forming a silicon nitride layer over the silicon dioxide layer;

forming at least one shallow trench isolation with an overhang by;

etching the silicon nitride layer, silicon dioxide layer and a portion of the silicon layer using a dry or wet etch process to form the at least one shallow trench isolation;

etching portions of the silicon nitride layer further back causing the silicon nitride layer to recede relative to side walls of the at least one shallow trench isolation sufficient to prevent oxidation in a determined portion of the device;

filling the at least one shallow trench isolation and receded areas with silicon dioxide;

planarizing a surface of the silicon dioxide; and

etching selective portions of the silicon nitride layer,

wherein the forming of the overhang is controlled by selectively applying a photoresist or hardmask to prevent etchant from undercutting determined areas during the etching portions step such that areas protected by the photoresist or hardmask do not exhibit pull-back required for formation of the overhang, and

wherein the overhang, in a first direction, is selectively configured to prevent bird'"'"'s beak formations where compressive stresses by the bird'"'"'s beak formations would degrade device performance.

8. The method of claim 7, wherein the overhang does not interfere with other structures on the device.

9. The method of claim 7, wherein the overhang extends beyond an STI-substrate interface by 0.01 to 0.5 microns.

10. The method of claim 7, wherein the silicon dioxide layer is deposited by chemical vapor deposition (CVD) or plasma CVD process.

11. The method of claim 10, wherein the silicon dioxide layer is planarized using reactive ion etching (RIE), chemical mechanical polishing, or a combination thereof.

12. The method of claim 7, wherein the silicon dioxide layer is about 2nm to 70nm thick and the silicon nitride layer is about 10 to 400 nm.

13. The method of claim 7, wherein the at least one shallow trench isolation structure is a T-shape or a stepped portion.

14. The method of claim 13, wherein the stepped portion overhangs a vertical silicon-silicon dioxide interface thereby inhibiting oxidation of the silicon of the interface.

15. The method of claim 7, wherein the overhang prevents oxidation by blocking access to the silicon layer.

16. A method of forming a device, comprising:

forming a silicon dioxide layer over a silicon layer;

forming a silicon nitride layer over the silicon dioxide layer;

forming at least one shallow trench isolation with an overhang by;

etching the silicon nitride layer, silicon dioxide layer and a portion of the silicon layer using a dry or wet etch process to form the at least one shallow trench isolation;

etching portions of the silicon nitride layer further back causing the silicon nitride layer to recede relative to side walls of the at least one shallow trench isolation sufficient to prevent oxidation in a determined portion of the device;

filling the at least one shallow trench isolation and receded areas with silicon dioxide;

planarizing a surface of the silicon dioxide; and

etching selective portions of the silicon nitride layer,

wherein the forming of the overhang is controlled by selectively applying a photoresist or hardmask to prevent etchant from undercutting determined areas during the etching portions step such that areas protected by the photoresist or hardmask do not exhibit pull-back required for formation of the overhang, and

wherein the overhang for nFET devices are in directions of and transverse to current flow.

17. The method of claim 16, wherein no overhang is formed in a direction parallel to a direction of current flow for pFET devices.