Semiconductor device having internal stress film

• US 7,205,615 B2
• Filed: 06/03/2004
• Issued: 04/17/2007
• Est. Priority Date: 06/16/2003
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tsutsui, Masafumi, Akamatsu, Kaori, Umimoto, Hiroyuki
• Primary Examiner(s): Weiss; Howard
• Application Number:
  US10/859,219
• Publication Number:
  US 20040251479A1
• Time in Patent Office: 1,048 Days
• Field of Search: 257/369
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

Claims

1. A semiconductor device, comprising an nMISFET and a pMISFET, wherein

the nMISFET includes:

a first active region which is divided by an isolation region formed in a semiconductor substrate made of silicon and which is made of the semiconductor substrate;

a first gate insulating film formed on the first active region;

a first gate electrode formed on the first gate insulating film;

n-type source/drain regions formed in regions of the first active region located on both sides of the first gate electrode; and

a first internal stress film formed on the n-type source/drain regions for generating a tensile stress in a gate length direction in a first channel region located in the first active region under the first gate electrode,

the pMISFET includes;

a second active region which is divided by the isolation region formed in the semiconductor substrate and which is made of the semiconductor substrate;

a second gate insulating film formed on the second active region;

a second gate electrode formed on the second gate insulating film;

p-type source/drain regions formed in regions of the second active region located on both sides of the second gate electrode; and

a second internal stress film formed on the p-type source/drain regions for generating a compressive stress in a gate length direction in a second channel region located in the second active region under the second gate electrode,

neither the first internal stress film nor the second internal stress film is formed on an upper surface of the first gate electrode and an upper surface of the second gate electrode.

2. The semiconductor device of claim 1, wherein

the first internal stress film is for generating the tensile stress in a substantially parallel direction to the gate length direction, and

the second internal stress film is for generating the compressive stress in a substantially parallel direction to the gate length direction.

3. The semiconductor device of claim 2, wherein

the substantially parallel direction of the tensile stress includes a direction tilted by an angle of less than 10 degree from a direction in which electrons move, and

the substantially parallel direction of the compressive stress includes a direction tilted by an angle of less than 10 degree from a direction in which electrons move.

4. The semiconductor device of claim 1, wherein

the first internal stress film and the second internal stress film are made of insulating films different from each other.

5. The semiconductor device of claim 1, wherein

the first internal stress film is made of a silicon nitride film, and

the second internal stress film is made of a TEOS film.

6. The semiconductor device of claim 1, wherein

the first internal stress film is directly in contact with the n-type source/drain regions, and

the second internal stress film is directly in contact with the p-type source/drain regions.

7. The semiconductor device of claim 1, wherein

the first internal stress film is formed above the n-type source/drain regions with a thin film interposed therebetween, and

the second internal stress film is formed above the p-type source/drain regions with a thin film interposed therebetween.

8. The semiconductor device of claim 1, wherein

at least one of the first internal stress film and the second internal stress film includes multiple layers.

9. The semiconductor device of claim 1, wherein

the n-type source/drain regions includes an n-type lightly doped impurity region, an n-type heavily doped impurity region and a suicide layer, and

the p-type source/drain regions includes a p-type lightly doped impurity region, a p-type heavily doped impurity region and a silicide layer.

10. The semiconductor device of claim 1, further comprising:

a first sidewall formed on a side surface of the first gate electrode, and

a second sidewall formed on a side surface of the second gate electrode.

11. The semiconductor device of claim 1, wherein

the first internal stress film is in contact with a side surface of the first gate electrode, and

the second internal stress film is in contact with a side surface of the second gate electrode.

12. The semiconductor device of claim 1, wherein

a principal surface of the semiconductor substrate is substantially a {100} plane, and

the gate length direction of each of the first gate electrode and the second gate electrode is substantially a <

011>

direction.