Semiconductor device and display comprising same

• US 7,205,640 B2
• Filed: 03/26/2003
• Issued: 04/17/2007
• Est. Priority Date: 05/22/2002
• Status: Expired due to Term

• Current Assignee: Hideo Ohno, Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), Masashi Kawasaki
• Original Assignee: Hideo Ohno, Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), Masashi Kawasaki
• Inventors: Sugihara, Toshinori, Kawasaki, Masashi, Hara, Takeshi, Ohno, Hideo, Fujita, Tatsuya, Ochi, Hisao, Yoshioka, Hiroto
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US10/515,120
• Publication Number:
  US 20050173734A1
• Time in Patent Office: 1,483 Days
• Field of Search: 257/765, 257/771, 257/E23.159, 257/E23.16, 257/E21.28, 257/614, 257/E33.19
• US Class Current: 257/646
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In an inverse-stagger MOSFET (1), a gate insulating layer (4) made of amorphous aluminum oxide is so formed as to face a channel layer (5) which serves as the semiconductor layer, and which is made of zinc oxide. With this arrangement, a defect level at an interface between the channel layer (5) and the gate insulating layer (4) is reduced, thereby obtaining performance equivalent to that of a semiconductor apparatus in which all the layered films are crystalline. This technique is applicable to a staggered MOSFET and the like, and has high versatility.

Claims

1. A semiconductor apparatus including a semiconductor layer that contains a group II oxide, comprising:

a layer made of amorphous aluminum oxide, on at least one surface of and directly contacting the semiconductor layer.

2. The semiconductor apparatus as set forth in claim 1, wherein:

the group II oxide is zinc oxide.

3. The semiconductor apparatus as set forth in claim 1, wherein:

the semiconductor layer is made of zinc oxide, and has a film thickness not less than 5 nm but not more than 100 nm.

4. The semiconductor apparatus as set forth in claim 1, wherein:

the amorphous aluminum oxide has resistance not less than 1×

10⁴ Ω

·

cm and not more than 2×

10¹⁷ Ω

·

cm.

5. A display apparatus, comprising:

the semiconductor apparatus as set forth in claim 1.

12. The semiconductor apparatus of claim 1, wherein the layer made of amorphous aluminum oxide is an insulating layer.

6. A semiconductor apparatus comprising:

a semiconductor layer that contains a group II oxide; and

a layer comprising amorphous aluminum oxide provided on and directly contacting at least one surface of the semiconductor layer.

7. The semiconductor apparatus of claim 6, wherein the semiconductor layer forms the channel of a transistor, and the layer comprising amorphous aluminum oxide is a gate insulating layer of the transistor.

8. The semiconductor apparatus of claim 6, wherein the group II oxide is zinc oxide.

9. The semiconductor apparatus of claim 6, wherein the semiconductor layer comprises zinc oxide and has a film thickness not less than 5 nm but not more than 100 nm.

10. The semiconductor apparatus of claim 6, wherein the amorphous aluminum oxide has resistance not less than 1×

10¹⁴ Ω

·

cm and not more than 2×

10¹⁷ Ω

·

cm.

11. A liquid crystal display apparatus comprising the semiconductor apparatus as set forth in claim 6, wherein the semiconductor layer forms the channel of a transistor, and the layer comprising amorphous aluminum oxide is a gate insulating layer of the transistor.

13. The semiconductor apparatus of claim 6, wherein the layer comprising amorphous aluminum oxide is an insulating layer.