Voltage regulator having a compensated load conductance

• US 7,205,828 B2
• Filed: 08/02/2004
• Issued: 04/17/2007
• Est. Priority Date: 08/02/2004
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Sridharan, Srinath
• Primary Examiner(s): Nguyen; Linh My
• Assistant Examiner(s): Hiltunen; Thomas J.
• Application Number:
  US10/909,849
• Publication Number:
  US 20060033555A1
• Time in Patent Office: 988 Days
• Field of Search: 327/538, 327/539, 327/540, 327/541, 327/543, 327/545, 327/546, 323/313, 323/315, 323/316, 323/280, 323/281
• US Class Current: 327/540
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A voltage regulator configured to provide a regulated voltage to a load having a first conductance is provided. The voltage regulator comprises a feedback circuit configured to generate the regulated voltage and a frequency compensation circuit comprising a first MOSFET device having a second conductance. The frequency compensation circuit is configured to operate the first MOSFET device so that the second conductance varies in response to the first conductance of the load.

Claims

1. A voltage regulator configured to provide a regulated voltage to a load having a first conductance, the voltage regulator comprising:

a feedback circuit configured to generate the regulated voltage; and

a frequency compensation circuit comprising a first MOSFET device having a second conductance;

wherein the frequency compensation circuit is configured to operate the first MOSFET device so that the second conductance varies in response to the first conductance of the load, wherein the feedback circuit comprises a second MOSFET device having a transconductance, wherein the frequency compensation circuit comprises a third MOSFET device having a third conductance, wherein the frequency compensation circuit is configured to operate the third MOSFET device so that the third conductance varies in response to the transconductance of the second MOSFET device, wherein the frequency compensation circuit comprises a first bias circuit and a second bias circuit, wherein the first bias circuit is configured to provide a first voltage to the third MOSFET device to cause the third conductance to vary in response to the transconductance of the second MOSFET device, wherein the second bias circuit is configured to provide a second voltage to the first MOSFET device to cause the second conductance to vary in response to the first conductance, wherein the first bias circuit comprises a fourth MOSFET device having a gate connection and a drain connection and a first current source connected to the gate connection, the drain connection, and a ground node, and wherein the first current source is configured to draw a first current from the fourth MOSFET device to generate the first voltage.

2. The voltage regulator of claim 1 wherein the second bias circuit comprises a fifth MOSFET device, a sixth MOSFET device, a seventh MOSFET device, a second current source, a third current source, and a resistive element having a first end and a second end, wherein the second current source is configured to draw a second current from the fifth MOSFET device through the resistor to generate a third voltage which is provided to the sixth MOSFET device, and wherein the third current source is configured to draw a third current from the sixth MOSFET device and the sixth seventh device to generate the second voltage.

3. The voltage regulator of claim 2 wherein the second current source is proportional to a master generated current source.

4. The voltage regulator of claim 2 wherein the third current source is proportional to a fourth current drawn by the load.

5. The voltage regulator of claim 1 wherein the feedback circuit further comprises a third bias circuit configured to provide a bias voltage to the second MOSFET device to control a feedback current though the second MOSFET device.

6. The voltage regulator of claim 1 wherein the feedback circuit further comprises a fifth MOSFET device, and wherein the fifth MOSFET device is configured to provide a load current to the load and the feedback current to the second MOSFET device.

7. The voltage regulator of claim 6 wherein the frequency compensation circuit further comprises a capacitive element having a first end connected to the fifth MOSFET device and a second end connected to the first MOSFET device and the third MOSFET device.

8. A system comprising:

a functional unit having a first conductance; and

a voltage regulator comprising;

a first circuit configured to provide a regulated voltage to the functional unit; and

a second circuit comprising a first MOSFET device having a second conductance;

wherein the second circuit is configured to operate the first MOSFET device so that the second conductance tracks the first conductance of the functional unit, wherein the first circuit comprises a second MOSFET device having a transconductance, wherein the second circuit comprises a third MOSFET device having a third conductance, wherein the second circuit is configured to operate the third MOSFET device so that the third conductance varies in response to the transconductance of the second MOSFET device, wherein the second circuit comprises a first bias circuit and a second bias circuit, wherein the first bias circuit is configured to provide a first voltage to the third MOSFET device to cause the third conductance to vary in response to the transconductance of the second MOSFET device, wherein the second bias circuit is configured to provide a second voltage to the first MOSFET device to cause the second conductance to vary in response to the first conductance, wherein the first bias circuit comprises a fourth MOSFET device having a gate connection and a drain connection and a first current source connected to the gate connection, the drain connection, and a ground node, and wherein the first current source is configured to draw a first current from the fourth MOSFET device to generate the first voltage.

9. The system of claim 8 further comprising:

a transceiver that comprises the functional unit.

10. The system of claim 9 wherein the transceiver is configured for use in a Global System for Mobile Communications (GSM) network.

11. The system of claim 8 wherein the second circuit is configured to operate the first MOSFET device in a linear region of the first MOSFET device.

12. The system of claim 8 wherein the second circuit comprises a second current source configured to generate a second current that is proportional to a third current provided to the functional unit, and wherein the second circuit is configured to generate the second voltage using the second current.

13. The system of claim 12 wherein the second circuit comprises a third current source configured to generate a fourth current that is proportional to a fifth current generated by a master calibrated current source, and wherein the second circuit is configured to generate the second voltage responsive to the fourth current.

14. The system of claim 8 wherein the first conductance varies over time.

15. A voltage regulator configured to provide a regulated voltage to a load having a first conductance, the voltage regulator comprising:

a feedback circuit configured to generate the regulated voltage; and

a frequency compensation circuit comprising a first MOSFET device having a second conductance;

wherein the frequency compensation circuit is configured to operate the first MOSFET device so that the second conductance varies in response to the first conductance of the load, wherein the feedback circuit comprises a second MOSFET device having a transconductance, wherein the frequency compensation circuit comprises a third MOSFET device having a third conductance, wherein the frequency compensation circuit is configured to operate the third MOSFET device so that the third conductance varies in response to the transconductance of the second MOSFET device, wherein the frequency compensation circuit comprises a first bias circuit and a second bias circuit, wherein the first bias circuit is configured to provide a first voltage to the third MOSFET device to cause the third conductance to vary in response to the transconductance of the second MOSFET device, wherein the second bias circuit is configured to provide a second voltage to the first MOSFET device to cause the second conductance to vary in response to the first conductance, wherein the second bias circuit comprises a fourth MOSFET device, a fifth MOSFET device, a sixth MOSFET device, a first current source, a second current source, and a resistive element having a first end and a second end, wherein the first current source is configured to draw a first current from the fourth MOSFET device through the resistor to generate a third voltage which is provided to the fifth MOSFET device, and wherein the second current source is configured to draw a second current from the fifth MOSFET device and the sixth MOSFET device to generate the second voltage.

16. The voltage regulator of claim 15 wherein the first bias circuit comprises a seventh MOSFET device having a gate connection and a drain connection and a third current source connected to the gate connection, the drain connection, and a ground node, and wherein third the current source is configured to draw a third current from the seventh MOSFET device to generate the first voltage.

17. The voltage regulator of claim 15 wherein the first current source is proportional to a master generated current source.

18. The voltage regulator of claim 15 wherein the second current source is proportional to a third current drawn by the load.

19. The voltage regulator of claim 15 wherein the feedback circuit further comprises a third bias circuit configured to provide a bias voltage to the second MOSFET device to control a feedback current though the second MOSFET device.

20. The voltage regulator of claim 15 wherein the feedback circuit further comprises a seventh MOSFET device, and wherein the seventh MOSFET device is configured to provide a load current to the load and the feedback current to the second MOSFET device.