Body effect amplifier

• US 7,205,837 B2
• Filed: 12/29/2003
• Issued: 04/17/2007
• Est. Priority Date: 12/29/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cohen, Ariel
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US10/749,930
• Publication Number:
  US 20050140441A1
• Time in Patent Office: 1,205 Days
• Field of Search: 330/253, 330/261
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45348 the AAC comprising one or more FETs with multiple gates
• CPC Class Codes: H03F 2203/45631 the LC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

A circuit includes a transistor having a biased gate terminal and an input coupled to a bulk terminal. A voltage applied between the bulk terminal and the source terminal modulates the drain-source current. The transistor operates in a saturation region with a bias voltage applied to the gate terminal. The output current is received by a load resistor or an active load.

Claims

1. A circuit comprising:

a differential pair to receive a differential signal at a bulk input port and to generate an output signal at an output port and

further including a common source/drain terminal of the differential pair coupled to a current source, and wherein a common gate of the differential pair is biased to operate the differential pair in a saturation mode.

2. A circuit comprising:

a differential pair to receive a differential signal at a bulk input port and to generate an output signal at an output port, the differential pair having a biased common gate and configured to operate in a saturation mode, and further including an amplifier coupled to the output port.

3. A circuit comprising:

a differential pair configured to operate in a saturation mode and configured to receive a differential signal at a bulk input port and to generate an output signal at an output port and further including an active load coupled to the drain output port and wherein the active load includes a transistor pair having a common gate.

4. A circuit comprising:

a first transistor having a first bulk and a first drain;

a first input node at the first bulk; and

a first output node at the first drain and wherein the first transistor includes a first source to receive a bias current and wherein the first transistor is biased to operate in a saturation mode.

5. A circuit comprising:

a first transistor having a first bulk and a first drain;

a first input node at the first bulk; and

a first output node at the first drain and wherein the first transistor includes a first source coupled to a supply voltage and wherein the first transistor is biased to operate in a saturation mode.

6. A circuit comprising:

a first transistor having a first bulk and a first drain;

a first input node at the first bulk; and

a first output node at the first drain; and

and further including

a second transistor having a second gate in common with the first gate, the second transistor having a second bulk and a second drain;

a second input node at the second bulk; and

a second output node at the second drain and wherein the first transistor and the second transistor are biased to operate in a saturation mode and include a common source.

7. The circuit of claim 6 further including a current source coupled to the common source/drain.

8. A method comprising:

biasing a gate terminal of a first transistor in an amplifier, wherein the first transistor is operated in a saturation mode;

providing an input signal to a bulk terminal of the first transistor; and

generating a first output signal as a function of the input signal at a first output terminal coupled to a first drain terminal of the amplifier and

wherein providing the input signal includes providing a first differential input signal to the first transistor of a differential pair and providing a second differential input signal to a second transistor of the differential pair, and further including biasing a source terminal of the first transistor.

9. The method of claim 8 wherein biasing the source terminal includes providing a current source.

10. A communication device comprising:

an antenna having an antenna output;

a first amplifier including a transistor having a bulk terminal coupled to the antenna output and a bias node coupled to a gate terminal of the transistor wherein the transistor is operated in a saturation mode; and

a second amplifier having an input coupled to a first drain node of the first amplifier and wherein the bulk terminal is coupled to the antenna output via a tuner.

11. A communication device comprising:

an antenna having an antenna output;

a first amplifier including a transistor having a bulk terminal coupled to the antenna output and a bias node coupled to a gate terminal of the transistor wherein the transistor is operated in a saturation mode; and

a second amplifier having an input coupled to a first drain node of the first amplifier and further including a second source terminal of the transistor coupled to a power supply.

12. The device of claim 11 wherein the power supply includes a current source.

13. A communication device comprising:

an antenna having an antenna output;

a first amplifier including a transistor having a bulk terminal coupled to the antenna output and a bias node coupled to a gate terminal of the transistor wherein the transistor is operated in a saturation mode; and

a second amplifier having an input coupled to a first drain node of the first amplifier and wherein the first amplifier includes a differential amplifier.