Pipelined analog to digital converter that is configurable based on mode and strength of received signal
First Claim
1. A pipelined Analog To Digital Converter (ADC), comprising:
- an input stage for sampling and holding an analog signal; and
a plurality of pipelined stages that are hierarchically arranged to resolve the analog signal into at least one of a plurality of bits in the digital representation of the analog signal, wherein a resolution for processing the digital representation by at least one of the plurality of stages is enabled by information that is based on the digital representation, and wherein the information indicates at least a strength that is associated with the analog signal, and wherein the resolution is controlled based on at least the strength.
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Accused Products
Abstract
A pipelined analog to digital converter (ADC) that is arranged to dynamically adapt its resolution and sampling frequency based on at least a determined mode of communication and the strength of a received wireless signal. Since standby mode data is typically communicated with a relatively low number of bits (low resolution), the ADC provides for disabling at least a portion of its pipelined stages that provide the higher resolution bits if the standby communication mode is detected. By lowering the ADC'"'"'s resolution for standby mode communication, it can conserve a considerable amount of power associated with the operation of the higher resolution bits. Similarly, relatively high resolution communication such as receiving and transmitting data and/or voice is process by the ADC by enabling sufficient pipelined stages to provide a higher number of bits.
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Citations
19 Claims
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1. A pipelined Analog To Digital Converter (ADC), comprising:
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an input stage for sampling and holding an analog signal; and a plurality of pipelined stages that are hierarchically arranged to resolve the analog signal into at least one of a plurality of bits in the digital representation of the analog signal, wherein a resolution for processing the digital representation by at least one of the plurality of stages is enabled by information that is based on the digital representation, and wherein the information indicates at least a strength that is associated with the analog signal, and wherein the resolution is controlled based on at least the strength. - View Dependent Claims (2, 3, 7, 9)
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4. A pipelined Analog To Digital Converter (ADC), comprising:
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an input stage for sampling and holding an analog signal; and a plurality of pipelined stages that are hierarchically arranged to resolve the analog signal into at least one of a plurality of bits in the digital representation of the analog signal, wherein a resolution for processing the digital representation by at least one of the plurality of stages is enabled by information that is based on the digital representation, and wherein the information indicates at least one of a mode or a strength that is associated with the analog signal, wherein the information is arranged in at least one frame, and wherein the resolution is controlled based on at least one of the mode or the strength. - View Dependent Claims (5)
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6. A pipelined Analog To Digital Converter (ADC), comprising:
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an input stage for sampling and holding an analog signal; and a plurality of pipelined stages that are hierarchically arranged to resolve the analog signal into at least one of a plurality of bits in the digital representation of the analog signal, wherein a resolution for processing the digital representation by at least one of the plurality of stages is enabled by information that is based on the digital representation, and wherein the information indicates at least one of a mode or a strength that is associated with the analog signal, wherein at least one of the mode and the strength of the analog signal are employed to disable at least one of the plurality of stages and change a value of the frequency for processing the analog signal.
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8. A pipelined Analog To Digital Converter (ADC), comprising:
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an input stage for sampling and holding an analog signal; and a plurality of pipelined stages that are hierarchically arranged to resolve the analog signal into at least one of a plurality of bits in the digital representation of the analog signal, wherein a resolution for processing the digital representation by at least one of the plurality of stages is enabled by information that is based on the digital representation, and wherein the information indicates at least one of a mode or a strength that is associated with the analog signal, wherein an output from each of the enabled stages is digitally correlated.
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10. A pipelined Analog To Digital Converter (ADC), comprising:
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an input stage for sampling and holding an analog signal; and a plurality of pipelined stages that are hierarchically arranged to resolve the analog signal into at least one of a plurality of bits in the digital representation of the analog signal, wherein a resolution for processing the digital representation by at least one of the plurality of stages is enabled by information that is based on the digital representation, and wherein the information indicates at least one of a mode or a strength that is associated with the analog signal, wherein the other indication is employed to enable at least one of the plurality of stages and change a frequency for processing the analog signal. - View Dependent Claims (11)
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12. A method for converting an analog signal into a digital representation of the analog signal, comprising:
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sampling the analog signal; hierarchically resolving the analog signal into a plurality of bits associated with the digital representation of the analog signal, wherein processing the analog signal with at least one of a plurality of stages is enabled by information determined from the digital representation, and wherein the information indicates at least a strength that is associated with the analog signals and wherein the processing is controlled based on at least the strength; and enabling an output of the digital representation of the analog signal. - View Dependent Claims (13, 14)
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15. A method for converting an analog signal into a digital representation of the analog signal, comprising:
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sampling the analog signal; hierarchically resolving the analog signal into a plurality of bits associated with the digital representation of the analog signal, wherein processing the analog signal with at least one of a plurality of stages is enabled by information determined from the digital representation, and wherein the information indicates at least one of a mode or a strength that is associated with the analog signal, and wherein the processing is controlled based on at least one of the mode or the strength; and enabling an output of the digital representation of the analog signal, wherein the information is arranged in at least one frame. - View Dependent Claims (16)
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17. A method for converting an analog signal into a digital representation of the analog signal, comprising:
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sampling the analog signal; hierarchically resolving the analog signal into a plurality of bits associated with the digital representation of the analog signal, wherein processing the analog signal with at least one of a plurality of stages is enabled by information determined from the digital representation, and wherein the information indicates at least one of a mode or a strength that is associated with the analog signal; and enabling an output of the digital representation of the analog signal, wherein a wireless protocol indicated by the determined information is employed to disable at least one of the plurality of stages.
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18. A pipelined Analog To Digital Converter (ADC), comprising:
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an input stage for sampling and holding an analog signal; and a plurality of pipelined stages that hierarchically resolve the analog signal into at least one of a plurality of bits associated with the digital representation of the analog signal, wherein a resolution and a frequency for processing the analog signal corresponds to the operation of a plurality of stages that are enabled based on information determined from the analog signal, and wherein the information indicates at least one of a mode and a strength of the analog signal. - View Dependent Claims (19)
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Specification