Image display apparatus

• US 7,205,965 B2
• Filed: 07/31/2003
• Issued: 04/17/2007
• Est. Priority Date: 12/19/2001
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Hitachi, Ltd.
• Inventors: Mikami, Yoshiro, Akimoto, Hajime, Ouchi, Takayuki, Satou, Toshihiro
• Primary Examiner(s): Liang; Regina
• Application Number:
  US10/630,706
• Publication Number:
  US 20040021620A1
• Time in Patent Office: 1,356 Days
• Field of Search: 345/76, 345/82, 345/90, 345/98, 345/204, 315/169.3, 315/169.1
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes

Abstract

An image display apparatus includes a plurality of scanning wires in an image display region for transmitting a scanning signal, a plurality of signal wires intersecting the plurality of scanning wires in the image display region for transmitting a signal voltage, a plurality of current driven electroooptical display elements each arranged in a pixel region surrounded by the wires connected to a common power supply, a plurality of driving elements in the pixel region connected with the electro-optical display elements and a plurality of memory control circuits for holding the signal voltage in response to the scanning signal to control driving of the driving elements based on the held signal voltage. The memory control circuit samples and holds the signal voltage while blocking a bias voltage from being applied to the driving elements, and subsequently applies the driving elements with the held signal voltage as the bias voltage.

Claims

1. An image display apparatus comprising:

a plurality of scanning wires arranged in an image display region for transmitting a scanning signal;

a plurality of signal wires arranged to intersect with said plurality of scanning wires in said image display region for transmitting a signal voltage;

a plurality of current driven electro-optical display elements each arranged in a pixel region surrounded by said scanning wires and said signal wires connected to a common power supply;

a plurality of driving elements arranged in said pixel region connected with said electro-optical display elements; and

a plurality of memory control circuits each including a sampling switch and a driving switch for holding said signal voltage in response to said scanning signal and to control driving of said driving elements based on said held signal voltage,

wherein said memory control circuit samples and holds said signal voltage while blocking a bias voltage from being applied to each of said driving elements by closing said sampling switch and opening said driving switch, and subsequently applies said held voltage signal to said driving elements as said bias voltage by opening said sampling switch and closing said driving switch.

2. An image display apparatus according to claim 1, wherein a power supply control element stops supplying the electric power to said driving elements.

3. An image display apparatus according to claim 1, wherein said memory control circuit comprises:

a main driving switch element responsive to said scanning signal to conduct for sampling said signal voltage; and

a sampling capacitor for holding the signal voltage sampled by said main sampling switch element.

4. An image display apparatus according to claim 1, wherein said memory control circuit comprises:

a main driving switch element responsive to said scanning signal to conductor for sampling said signal voltage;

a sampling capacitor for holding the signal voltage sampled by said main sampling switch element; and

an auxiliary driving switch element responsive to said scanning signal to conduct for connecting one end of said sampling capacitor to a common electrode.

5. An image display apparatus according to claim 1, wherein said current driven electro-optical display elements comprise organic LEDs.

6. An image display apparatus comprising:

a plurality of scanning wires arranged in an image display region for transmitting a scanning signal;

a plurality of signal wires arranged to intersect with said plurality of scanning wires in said image display region for transmitting a signal voltage;

a plurality of current driven electro-optical display elements arranged in a pixel region surrounded by said scanning wires and said signal wires connected to a common power supply;

a plurality of driving elements arranged in said pixel region connected with said electro-optical display elements; and

a plurality of memory control circuits each including a sampling switch and a driving switch for holding said signal voltage in response to said scanning signal and to control driving of said driving elements based an said held signal voltage,

wherein said memory control circuit samples and holds said signal voltage in a sampling period by closing said sampling switch and opening said driving switch; and

subsequently applied said held voltage signal to said driving elements by opening said sampling switch; and

closing said driving; and

wherein a voltage applied to said driving elements in said sampling period is lower than a voltage in a write period.

7. An image display apparatus according to claim 6, wherein said driving elements are non-conductive in said sampling period.

8. An image display apparatus according to claim 6, wherein said memory control circuit comprises:

a main driving switch element responsive to said scanning signal to conduct for sampling said signal voltage; and

a sampling capacitor for holding the signal voltage sampled by said main sampling switch element.

9. An image display apparatus according to claim 6, wherein said memory control circuit comprises:

a main driving switch element responsive to said scanning signal to conduct for sampling said signal voltage;

a sampling capacitor for holding the signal voltage sampled by said main sampling switch element; and

an auxiliary driving switch element responsive to said scanning signal to conduct for connecting one end of said sampling capacitor to a common electrode.

10. An image display apparatus according to claim 6, wherein said current driven electro-optical display elements comprise organic LEDs.

11. An image display apparatus comprising:

a plurality of scanning wires arranged in an image display region for transmitting a scanning signal;

a plurality of signal wires arranged to intersect with said plurality of scanning wires in said image display region for transmitting a signal voltage;

a plurality of current driven electro-optical display elements arranged in a pixel region which is surrounded by said scanning wires and said signal wires connected to a common power supply;

a plurality of driving elements arranged in said pixel region connected with said electro-optical display elements;

a plurality of memory control circuits each including a sampling switch and a driving switch for holding said signal voltage in response to said scanning signal and to control driving of said driving elements based on said held signal voltage;

a power supply control element for controlling electric power supplied from said common power supply to said driving elements,

wherein said memory control circuit samples and holds said signal voltage in a sampling period by closing said sampling switch and opening said driving switch; and

subsequently applied said held voltage signal to said driving elements by opening said sampling switch and closing said driving switch; and

the electric power supplied to said driving elements in said sampling period is lower than the electric power in a write period.

12. An image display apparatus according to claim 11, wherein said memory control circuit comprises:

a main driving switch element responsive to said scanning signal to conduct for sampling said signal voltage; and

a sampling capacitor for holding the signal voltage sampled by said main sampling switch element.

13. An image display apparatus according to claim 11, wherein said memory control circuit comprises:

a main driving switch element responsive to said scanning signal to conduct for sampling said signal voltage;

a sampling capacitor for holding the signal voltage sampled by said main sampling switch element; and

an auxiliary driving switch element responsive to said scanning signal to conduct for connecting one end of said sampling capacitor to a common electrode.

14. An image display apparatus according to claim 11, wherein said current driven electro-optical display elements comprise organic LEDs.