Frame assembly circuit for use in a scalable shared queuing switch and method of operation

• US 7,206,325 B2
• Filed: 05/08/2002
• Issued: 04/17/2007
• Est. Priority Date: 05/08/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Nong, Ge
• Primary Examiner(s): Sam; Phirin
• Application Number:
  US10/141,560
• Publication Number:
  US 20030210687A1
• Time in Patent Office: 1,805 Days
• Field of Search: None
• US Class Current: 370/474
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction

Abstract

A packet switch capable of receiving fixed size data cells from N input ports and transmitting the fixed size data cells to N output ports. The packet switch comprises: 1) a frame deserializer for receiving the data cells as serial bits from the N input ports and transmitting the data cells as parallel bits in data frames containing a plurality of data cells, wherein each of the plurality of data cells in each data frame are destined for a common output port; 2) a frame serializer for receiving the data frames and transmitting the plurality of data cells in the data frames as serial bits to the N output ports; and 3) a shared buffer coupling the frame deserializer and the frame serializer for receiving and buffering the data frames from the frame deserializer and transmitting the buffered data frames to the frame serializer.

Claims

1. A packet switch capable of receiving fixed size data cells from N input ports and transmitting said fixed size data cells to N output ports, said packet switch comprising:

a frame deserializer capable of receiving said data cells as serial bits from said N input ports and transmitting said data cells as parallel bits in data frames containing a plurality of data cells, wherein each of said plurality of data cells in each data frame are destined for a common output port;

a frame serializer capable of receiving said data frames and transmitting said plurality of data cells in said data frames as serial bits to said N output ports; and

a shared buffer coupling said frame deserializer and said frame serializer capable of receiving and buffering said data frames from said frame deserializer and transmitting said buffered data frames to said frame serializer.

2. The packet switch as set forth in claim 1 wherein each said data frame contains up to N data cells.

3. The packet switch as set forth in claim 2 wherein said frame deserializer transmits to said shared buffer fully filled data frames containing N data cells prior to transmitting partially filled data frames containing less than N data cells.

4. The packet switch as set forth in claim 3 wherein said frame deserializer first transmits to said shared buffer a first fully filled data frame having a highest priority among all fully filled data frames.

5. The packet switch as set forth in claim 4 wherein a priority of each of said fully filled data frames is determined by a priority of said common output port associated with each of said fully filled data frames.

6. The packet switch as set forth in claim 5 wherein a priority of a first common output port to which said first fully filled data frame is transmitted is updated after said first fully filled data frame has been transmitted.

7. The packet switch as set forth in claim 3 wherein said frame deserializer first transmits to said shared buffer a first partially filled data frame having a highest priority among all partially filled data frames.

8. The packet switch as set forth in claim 7 wherein a priority of each of said partially filled data frames is determined by a priority of said common output port associated with each of said partially filled data frames.

9. The packet switch as set forth in claim 8 wherein a priority of a first common output port to which a first of said partially filled data frames is transmitted is updated after said first partially filled data frame has been transmitted.

10. The packet switch as set forth in claim 1 wherein said frame deserializer comprises a frame assembly buffer comprising:

N input buffers capable of receiving and buffering said data cells from said N input ports;

N output buffers capable of receiving and storing said data cells transferred from said N input buffers; and

an interconnection network capable transferring said data cells from each of said N input buffers to each of said output buffers.

11. The packet switch as set forth in claim 1 wherein said shared buffer comprises a plurality of shared buffer banks.

12. A communication network capable of transferring data in fixed-size packets between a plurality of end-user devices, said communication network comprising:

a plurality of packet switches, each of said packet switches capable of receiving fixed size data cells from N input ports and transmitting said fixed size data cells to N output ports, said each packet switch comprising;

a frame deserializer capable of receiving said data cells as serial bits from said N input ports and transmitting said data cells as parallel bits in data frames containing a plurality of data cells, wherein each of said plurality of data cells in each data frame are destined for a common output port;

a frame serializer capable of receiving said data frames and transmitting said plurality of data cells in said data frames as serial bits to said N output ports; and

a shared buffer coupling said frame deserializer and said frame serializer capable of receiving and buffering said data frames from said frame deserializer and transmitting said buffered data frames to said frame serializer.

13. The communication network as set forth in claim 12 wherein each said data frame contains up to N data cells.

14. The communication network as set forth in claim 13 wherein said frame deserializer transmits to said shared buffer fully filled data frames containing N data cells prior to transmitting partially filled data frames containing less than N data cells.

15. The communication network as set forth in claim 14 wherein said frame deserializer first transmits to said shared buffer a first fully filled data frame having a highest priority among all fully filled data frames.

16. The communication network as set forth in claim 15 wherein a priority of each of said fully filled data frames is determined by a priority of said common output port associated with each of said fully filled data frames.

17. The communication network as set forth in claim 16 wherein a priority of a first common output port to which said first fully filled data frame is transmitted is updated after said first fully filled data frame has been transmitted.

18. The communication network as set forth in claim 14 wherein said frame deserializer first transmits to said shared buffer a first partially filled data frame having a highest priority among all partially filled data frames.

19. The communication network as set forth in claim 18 wherein a priority of each of said partially filled data frames is determined by a priority of said common output port associated with each of said partially filled data frames.

20. The communication network as set forth in claim 19 wherein a priority of each of said partially filled data frames is determined by a priority of said common output port associated with each of said partially filled data frames.

21. The communication network as set forth in claim 12 wherein said frame deserializer comprises a frame assembly buffer comprising:

N input buffers capable of receiving and buffering said data cells from said N input ports;

N output buffers capable of receiving and storing said data cells transferred from said N input buffers; and

an interconnection network capable transferring said data cells from each of said N input buffers to each of said output buffers.

22. The communication network as set forth in claim 12 wherein said shared buffer comprises a plurality of shared buffer banks.

23. A method of operating a packet switch capable of receiving fixed size data cells from N input ports and transmitting the fixed size data cells to N output ports, the method comprising the steps of:

receiving the data cells in a frame deserializer as serial bits from the N input ports;

transmitting the data cells to a shared buffer as parallel bits in data frames containing a plurality of data cells, wherein each of the plurality of data cells in each data frame are destined for a common output port;

receiving and buffering in the shared buffer the data frames from the frame deserializer;

transmitting the buffered data frames to a frame serializer; and

receiving the data frames in the frame serializer and transmitting the plurality of data cells in the data frames as serial bits to the N output ports.

24. The method as set forth in claim 23 wherein each data frame contains up to N data cells.

25. The method as set forth in claim 24 wherein the step of transmitting the data cells to the shared buffer comprises the substep of transmitting to the shared buffer fully filled data frames containing N data cells prior to transmitting partially filled data frames containing less than N data cells.

26. The method as set forth in claim 25 further comprising the substep of first transmitting to the shared buffer a first fully filled data frame having a highest priority among all fully filled data frames.

27. The method as set forth in claim 26 wherein a priority of each of the fully filled data frames is determined by a priority of the common output port associated with each of the fully filled data frames.

28. The method as set forth in claim 27 wherein a priority of a first common output port to which the first fully filled data frame is transmitted is updated after the first fully filled data frame has been transmitted.

29. The method as set forth in claim 25 wherein the step of transmitting the data cells to the shared buffer comprises the substep of first transmitting to the shared buffer a first partially filled data frame having a highest priority among all partially filled data frames.

30. The method as set forth in claim 29 wherein a priority of each of the partially filled data frames is determined by a priority of the common output port associated with each of the partially filled data frames.

31. The method as set forth in claim 30 wherein a priority of a first common output port to which a first of the partially filled data frames is transmitted is updated after the first partially filled data frame has been transmitted.