Host to FPGA interface in an in-circuit emulation system
First Claim
1. A method comprising:
- establishing an interface between a host computer and a general purpose programmable hardware device;
transmitting configuration information over said interface in a first transmission mode to configure the general purpose programmable hardware device to function according to a programmed configuration as virtual device under test; and
transmitting operation information from said virtual device under test emulating operation of an actual device under tests and operation information from said actual device under test over said interface in a second transmission mode.
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Accused Products
Abstract
A multi-purpose interface between a host computer and an FPGA. This interface uses an IEEE 1284 compliant EPP mode connection. When the host computer is initialized, a reset of the FPGA is carried out to clear the configuration memory of the FPGA. The data lines of the interface are then used to communicate unidirectional configuration data into the FPGA. The data are clocked by the host computer using the data strobe signal line to clock data into the FPGA. When the FPGA has been fully programmed, including programming an IEEE 1284 compliant EPP mode interface into the FPGA, the data lines are used for bidirectional communication between the host computer and the configured FPGA, in this embodiment operating as a virtual microcontroller.
75 Citations
18 Claims
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1. A method comprising:
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establishing an interface between a host computer and a general purpose programmable hardware device; transmitting configuration information over said interface in a first transmission mode to configure the general purpose programmable hardware device to function according to a programmed configuration as virtual device under test; and transmitting operation information from said virtual device under test emulating operation of an actual device under tests and operation information from said actual device under test over said interface in a second transmission mode. - View Dependent Claims (2, 3, 4)
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5. A method comprising:
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communicating configuration information between a host computer and a virtual device under test (DUT) to configure the virtual DUT to emulate a DUT; executing instructions in synchronization on the DUT and the virtual DUT; and transmitting operation information, from said executing by the DUT and the virtual DUT, between the host computer and the virtual DUT. - View Dependent Claims (6, 7, 8, 9)
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10. A method comprising:
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connecting a host computer to a base station using a communication interface, wherein the base station includes a field programmable gate array (FPGA); programming an emulator configuration into the FPGA using the communication interface; and receiving operation information from a device under test (DUT) and the FPGA emulating the DUT using the communication interface. - View Dependent Claims (11, 12, 13, 14)
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15. A method comprising:
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transmitting interface information over a parallel communication interface of a field programmable gate array (FPGA) to configure the FPGA to act as a parallel port; transmitting emulator information to the FPGA to configure the FPGA to operate as a virtual microcontroller in lock step with a microcontroller under test using the parallel port of the FPGA; and receiving operation information, generated by the virtual microcontroller and the microcontroller under test operating in lock step, from the parallel port of the FPGA. - View Dependent Claims (16, 17, 18)
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Specification