System and method for memory hub-based expansion bus

• US 7,206,887 B2
• Filed: 04/07/2006
• Issued: 04/17/2007
• Est. Priority Date: 03/25/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Ray; Gopal C.
• Application Number:
  US11/399,873
• Publication Number:
  US 20060179208A1
• Time in Patent Office: 375 Days
• Field of Search: 710/100, 710/300, 710/104, 710/311, 710/5, 710/303, 710/2, 710/305, 710/316, 712/11, 712/15, 712/34, 712/220, 365/63, 365/52, 365/230.01, 361/679, 361/684, 345/418, 370/351, 370/338, 370/423, 370/912, 711/105, 711/119, 711/5, 711/149, 713/400, 709/201, 709/219
• US Class Current: 710/311
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: Y10S 370/912 Packet communications

Abstract

A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Claims

1. A method of configuring a system memory, comprising:

providing a memory module having a plurality of memory devices coupled to a memory hub, the memory hub adapted to receive memory command packets and access the memory devices according to the memory command packets and further adapted to provide memory responses in response thereto, the memory hub including

a switch circuit having a plurality of switch nodes and adapted to couple any one switch node to another switch node,

a plurality of link interface circuits, each link interface circuit having a first node coupled to a respective one of the plurality of switch nodes and further having a second node coupled to either the first or second portions of the memory bus, each link interface circuit coupling signals from its first node to its second node,

a memory controller coupled to a switch node of the switch circuit to receive memory command packets and translate the same into memory device command signals, and

a local memory bus coupled to the memory controller and the memory devices on which the memory device command signals are provided;

coupling the memory hub of the memory module to a first portion of a memory bus coupled to a system controller, the system controller adapted to provide memory requests to access the memory devices on the first portion of the memory bus and receive memory responses from the memory hub on the first portion of the memory bus; and

coupling an expansion module having a processor circuit located thereon to a second portion of the memory bus coupled to the memory hub, the processor circuit adapted to provide memory requests on the second portion of the memory bus to the memory hub to access the memory devices of the memory module and further adapted to process data included in the memory responses provided on the second portion of the memory bus from the memory hub.

2. The method of claim 1 wherein coupling the memory hub of the memory module to the first portion of a memory bus coupled to a system controller comprises coupling the memory hub to a unidirectional downstream bus coupled to the system controller to which memory requests from the system controller are coupled and further coupling the memory hub to a unidirectional upstream bus coupled to the system controller to which memory responses from the memory hub to the system controller are coupled.

3. The method of claim 1 wherein coupling the expansion module to the second portion of the memory bus coupled to the memory hub comprises coupling the processor circuit to a unidirectional downstream bus coupled to the memory hub to which memory responses from the memory hub to the processor circuit located on the expansion module are coupled and further coupling the processor circuit to a unidirectional upstream bus coupled to the memory hub to which memory requests from the processor circuit to the memory hub are coupled.

4. The method of claim 1 wherein coupling the expansion module having the processor circuit located thereon to the second portion of the memory bus coupled to the memory hub comprises coupling an expansion module having a graphics controller for processing graphics data stored in the memory devices of the memory module.

5. The method of claim 1 wherein coupling the expansion module having the processor circuit located thereon to the second portion of the memory bus coupled to the memory hub comprises coupling an expansion module having an input/output processor adapted to process input data and storing the same in the memory devices of the memory module and further adapted to process output data stored in the memory devices of the memory module.