Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results

• US 7,207,017 B1
• Filed: 06/10/2004
• Issued: 04/17/2007
• Est. Priority Date: 06/10/2004
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Spence, Christopher A., Tabery, Cyrus, Haidinyak, Chris, Lukanc, Todd P., Capodieci, Luigi, Babcock, Carl P., Kim, Hung-Eil
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): BOWERS, BRANDON
• Application Number:
  US10/865,047
• Time in Patent Office: 1,041 Days
• Field of Search: 716/4
• US Class Current: 716/52
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

Claims

1. A method of generating a metrology recipe, the method comprising:

identifying regions of interest within a device layout;

creating a table of coordinates corresponding to the identified regions of interest;

creating a clipped layout data file by selectively extracting layout data clips from a layout file representative of the device layout, wherein the clipped layout data file is representative of a layout having the identified regions of interest in locations corresponding to the coordinate table and wherein the remainder of the layout represented by the clipped layout file is empty; and

outputting the clipped layout data file and the table of coordinates and at least a portion of the device layout to at least one metrology testing device.

2. The method of claim 1, further comprising:

converting the at least a portion of the device layout and the table of coordinates into a metrology recipe.

3. The method of claim 1, further comprising:

converting the clipped layout data file and the table of coordinates into a metrology recipe.

4. The method of claim 3, wherein the converting step includes:

receiving at least one of text files and Extensible Markup Language (XML) files corresponding to the clipped layout data file and the table of coordinates; and

converting the received files into a metrology recipe in a vendor proprietary binary format.

5. The method of claim 1, wherein the identifying step includes:

simulating how the device layout will pattern on a wafer; and

performing optical rule checking (ORC) on the simulated device layout.

6. The method of claim 5, wherein the identifying step includes:

identifying structures within the simulated layout that are (i) not within predefined specification limits or (ii) marginally within predefined specification limits.

7. The method of claim 6, wherein the identifying step includes:

identifying regions of the device layout that include test structures.

8. The method of claim 7, wherein the identifying step includes:

identifying regions of the device layout based on design attribute information.

9. The method of claim 1, wherein the metrology testing device includes at least one of a microscopy device, an electrical metrology device and an optical metrology device.

10. The method of claim 9, wherein the metrology testing device tests at least one of wafer metrology and reticle metrology.

11. A method of generating a metrology recipe, the method comprising:

identifying regions of interest within a device layout;

creating a table of coordinates corresponding to the identified regions of interest;

creating a clipped layout data file, by selectively extracting layout data clips from a layout file representative of the device layout, wherein the clipped layout data file is representative of a layout having the identified regions of interest in locations corresponding to the coordinate table and wherein the remainder of the layout represented by the clipped layout file is empty;

performing a simulation of how the clipped regions of interest will pattern on a wafer; and

outputting the simulation along with the clipped layout data file and table of coordinates to at least one metrology testing device.

12. A program embodied in a computer-readable medium, wherein when the program is loaded in memory on a computer and executed causes the computer to automatically generate a metrology recipe by:

identifying regions of interest within a device layout;

creating a table of coordinates corresponding to the identified regions of interest;

creating a clipped layout data file, by selectively extracting layout data clips from a layout file representative of the device layout, wherein the clipped layout data file is representative of a layout having the identified regions of interest in locations corresponding to the coordinate table and wherein the remainder of the layout represented by the clipped layout file is empty; and

converting the clipped layout data file and the table of coordinates into a metrology recipe;

performing a simulation of how the clipped regions of interest will pattern on a wafer; and

outputting the simulation along with the clipped layout data file and table of coordinates to at least one metrology testing device.

13. The program of claim 12, wherein the program causes the computer to:

transmit the metrology recipe to at least one metrology testing device.

14. The program of claim 12, wherein the program causes the computer to:

receive at least one of text files and Extensible Markup Language (XML) files corresponding to the clipped layout data file and the table of coordinates; and

convert the received files into a metrology recipe in a vendor proprietary binary format.

15. The program of claim 12, wherein the program causes the computer to:

receive experimental metrology results from at least one metrology tool based on the metrology recipe; and

link the experimental metrology results to at least one of design data, layout data and simulation data in a queriable database.

16. A method of designing an integrated circuit (IC) device, said method comprising:

generating a layout corresponding to an IC device design;

simulating how structures within the layout will pattern on a wafer;

identifying regions of interest within the layout;

creating a coordinate list, said coordinate list corresponding to locations within the layout of each region of interest;

creating a clipped layout file by selectively extracting layout data clips from a layout file representative of the device layout, wherein the clipped layout data file is representative of a layout having the identified regions of interest in locations corresponding to the coordinate table and wherein the remainder of the layout represented by the clipped layout file is empty;

converting the clipped layout file and the coordinate list into a metrology recipe;

sending the metrology recipe to at least one metrology tool;

receiving experimental metrology results from the at least one metrology tool based on the sent metrology recipe; and

linking the experimental metrology results to at least one of design data, layout data and simulation data in a queriable database.

17. The method of claim 16, said method further comprising:

performing optical proximity corrections (OPC) on the layout.

18. The method of claim 17, said method further comprising:

using the experimental metrology results to provide feedback at least one of the layout, OPC and simulation steps.

19. The method of claim 16, wherein the step of identifying regions of interest includes, based on the simulating step, identifying regions of the simulated layout that include structures that are (i) not within predefined specification limits or (ii) marginally within predefined specification limits.

20. The method of claim 16, wherein the step of linking includes selectively storing the results in a queriable database system along with at least one of design data, layout data and simulation data.

21. The method of claim 16, wherein the metrology recipe includes instructions for at least one of microscopy, electrical metrology and optical metrology.

22. The method of claim 16, wherein the converting step includes converting files and lists into a customized binary format for automated metrology testing by the at least one metrology tool.

23. The method of claim 16, wherein the queriable database comprises a queriable database system for controlling and storing data related to integrated circuit (IC) device design and manufacture, the database system comprising:

design data, simulation data and experimental data that is stored and coordinated based on data indicative of a physical representation of the design data.

24. The method of claim 23, wherein the database system is queriable based on a plurality of experimental input functions.

25. The method of claim 24, wherein the experimental input functions include at least one of design parameters, mask design parameters, exposure conditions and process conditions.