Ink jet printhead nozzle arrangement with actuated nozzle chamber closure

• US 7,207,657 B2
• Filed: 07/21/2005
• Issued: 04/24/2007
• Est. Priority Date: 07/15/1997
• Status: Expired due to Fees

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia
• Primary Examiner(s): Do; An H.
• Application Number:
  US11/185,720
• Publication Number:
  US 20050264611A1
• Time in Patent Office: 642 Days
• Field of Search: 347/54, 347/56, 347/65
• US Class Current: 347/54
• CPC Class Codes: B41J 2/14427 Structure of ink jet print heads with thermal bend detached actuators
• CPC Class Codes: B41J 2/1623 bonding and adhesion
• CPC Class Codes: B41J 2/1626 etching
• CPC Class Codes: B41J 2/1628 dry etching
• CPC Class Codes: B41J 2/1629 wet etching
• CPC Class Codes: B41J 2/1631 photolithography
• CPC Class Codes: B41J 2/1632 machining
• CPC Class Codes: B41J 2/1635 dividing the wafer into individual chips
• CPC Class Codes: B41J 2/1637 molding
• CPC Class Codes: B41J 2/1639 sacrificial molding
• CPC Class Codes: B41J 2/1642 thin film formation by CVD [chemical vapor deposition]
• CPC Class Codes: B41J 2/1643 thin film formation by plating
• CPC Class Codes: B41J 2/1645 thin film formation by spincoating
• CPC Class Codes: B41J 2/1646 thin film formation by sputtering
• CPC Class Codes: B41J 2/1648 Production of print heads with thermal bend detached actuators
• CPC Class Codes: B41J 2/16585 for paper-width or non-reciprocating print heads
• CPC Class Codes: B41J 2/17503 Ink cartridges
• CPC Class Codes: B41J 2/17513 Inner structure
• CPC Class Codes: B41J 2/17596 Ink pumps, ink valves
• CPC Class Codes: B41J 2002/041 Electromagnetic transducer
• CPC Class Codes: B41J 2202/21 : Line printing
• CPC Class Codes: B41J 3/445 : Printers integrated in other types of apparatus, e.g. printers integrated in cameras
• CPC Class Codes: B82Y 30/00 : Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G06F 21/79 : in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/86 : Secure or tamper-resistant housings
• CPC Class Codes: G06F 2221/2129 : Authenticate client device independently of the user
• CPC Class Codes: G06K 1/121 : by printing code marks applying code marks to labels B65C9/46; marking or coding completed packages B65B61/26
• CPC Class Codes: G06K 19/06037 : multi-dimensional coding
• CPC Class Codes: G06K 19/073 : Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 7/14 : using light without selection of wavelength, e.g. sensing reflected white light G06K7/10831 - G06K7/1097 take precedence
• CPC Class Codes: G06K 7/1417 : 2D bar codes
• CPC Class Codes: G11C 11/56 : using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: H04N 1/2112 : using still video cameras
• CPC Class Codes: H04N 1/2154 : the still video camera incorporating a hardcopy reproducing device, e.g. a printer
• CPC Class Codes: H04N 2101/00 : Still video cameras
• CPC Class Codes: H04N 23/00 : Cameras or camera modules comprising electronic image sensors; Control thereof
• CPC Class Codes: H04N 5/2628 : Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

A nozzle arrangement for an ink jet printhead chip comprises a wafer substrate having a front surface, a rear surface and a nozzle chamber extending through the wafer substrate to define an inlet at the rear surface of the wafer substrate. An outlet is defined at the front surface of the wafer substrate. The nozzle chamber is in fluid communication with an ink supply at the rear surface of the wafer substrate. A closure member is positioned on the rear surface of the substrate and is displaceable between open and closed positions to control a flow of ink through the wafer substrate. An actuator is operatively engaged with the closure member to displace the closure member between the open and closed positions when activated.

Claims

1. A nozzle arrangement for an ink jet printhead chip, the nozzle arrangement comprising

a wafer substrate having a front surface, a rear surface and a nozzle chamber extending through the wafer substrate to define an inlet at the rear surface of the wafer substrate and an outlet at the front surface of the wafer substrate, the nozzle chamber being in fluid communication with an ink supply at the rear surface of the wafer substrate;

a closure member positioned on the rear surface of the substrate and being displaceable between open and closed positions to control a flow of ink through the wafer substrate; and

an actuator operatively engaged with the closure member to displace the closure member between the open and closed positions, when activated;

wherein,

the chamber, the outlet and the actuator are dimensioned with respect to the ink properties such that the ink is retained within the chamber when the closure member is in the closed position by the ink surface across the outlet.

2. A nozzle arrangement as claimed in claim 1, in which the rear surface is substantially planar and the closure member is constrained to move in a plane substantially parallel to the rear surface.

3. A nozzle arrangement as claimed in claim 2, in which the closure member is constrained to move between the open and closed positions along a linear path.

4. A nozzle arrangement as claimed in claim 1, wherein the actuator engages the closure member via a gear train.

5. A nozzle arrangement as claimed in claim 4, wherein the gear train includes at least one rotating gear wheel and a linear gear positioned on the closure member.

6. A nozzle arrangement as claimed in claim 1, in which a drive circuitry layer is positioned on the rear surface of the wafer substrate and is electrically connected to the actuator, so tat the actuator can be activated by a signal received from the drive circuitry layer.