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Method and system for analyzing defects of an integrated circuit wafer

  • US 7,208,328 B2
  • Filed: 03/16/2004
  • Issued: 04/24/2007
  • Est. Priority Date: 03/16/2004
  • Status: Active Grant
First Claim
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1. A method for analyzing defects of an integrated circuit wafer in the manufacture of the wafer, comprising:

  • inspecting the wafer to automatically identify a plurality of defects;

    classifying defects from the plurality of defects into a plurality of groups including a first and a second group, the first group including only defects having a reported size that is at least as small as a first predetermined size and the second group including only defects having a reported size that is at least as large as the first predetermined size;

    selecting for further review, defects from the second and first groups respectively in a ratio of Ny;

    Nx, where Ny/Nx is larger than the ratio of the number of defects in the second group to the number of defects in the first group.

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