Bonding gate oxide with high-k additives

• US 7,208,366 B2
• Filed: 08/12/2004
• Issued: 04/24/2007
• Est. Priority Date: 04/28/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tsai, Wilman
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US10/917,886
• Publication Number:
  US 20050012164A1
• Time in Patent Office: 985 Days
• Field of Search: 438/197, 438/216, 438/240, 438/785, 438/287, 438/591
• US Class Current: 438/216
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A technique for producing a thin gate oxide having a relatively high dielectric constant. Embodiments relate to the structure and development of a gate oxide having a thickness of less than 1 nm, having a dielectric constant greater than twenty, and being substantially free of undesired electrical characteristics caused by exposure of the gate oxide to high complementary metal-oxide-semiconductor processing temperatures.

Claims

1. A process comprising:

forming a gate oxide, the gate oxide comprising ZrO₂ and HfO₂;

bonding the gate oxide with high-k additives, the high-k additives comprising Y₂O₃, La₂O₃, and TiO₂;

curing oxygen-deficient defects in the gate oxide while minimizing interfacial oxide growth;

promoting thermal stability during CMOS processing at high temperatures greater than 1000 C, and

forming a combined dielectric, the combined dielectric having a thickness of less than 1 nm, the combined dielectric having a dielectric constant of greater than twenty, the combined dielectric not displaying fixed charge problems, and the combined dielectric having a high crystallization onset to remain substantially amorphous.

2. The process of claim 1 wherein the gate oxide is annealed by exposing the gate oxide to a low-oxygen ambient atmosphere at a pressure range that is less than 1×

10<sup>−

3</sup> Torr.

3. The process of claim 2 wherein the gate oxide is doped with nitrogen by a process chosen from a group consisting of plasma nitridation, thermal nitrogen ambient anneal, and implantation.

4. The process of claim 3 wherein the nitrogen ambient includes a compound chosen from a group consisting of NH₃, NO, NO₂, and N₂.