Non-volatile semiconductor memory device allowing shrinking of memory cell

• US 7,208,751 B2
• Filed: 03/18/2003
• Issued: 04/24/2007
• Est. Priority Date: 09/13/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ooishi, Tsukasa
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US10/389,753
• Publication Number:
  US 20040051094A1
• Time in Patent Office: 1,498 Days
• Field of Search: 257/5, 257/3, 257/4, 361/200, 361/163, 361/185.02, 361/185.03, 361/105
• US Class Current: 257/5
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.

Claims

1. A non-volatile semiconductor memory device comprising:

a plurality of bit lines each arranged extending in a column direction;

a plurality of memory cells, arranged in rows and columns and disposed such that said plurality of bit lines are arranged corresponding to the respective columns of the memory cells, each being connected to the bit line of a corresponding column, and including a phase change element being substantially identical in width in a row direction to the bit line on a corresponding column and having a crystalline state thereof changed according to stored data; and

a plurality of word lines arranged corresponding to the rows of the memory cells, each coupled to the memory cells on a corresponding row and formed of an impurity region coupled to the phase change elements on the corresponding row.

2. The non-volatile semiconductor memory device according to claim 1, wherein said phase change element of each memory cell is formed in self alignment to the bit line on a corresponding column.

3. A non-volatile semiconductor memory device comprising:

a plurality of memory cells, arranged in rows and columns, each including a variable resistance element having a resistance value set in accordance with stored data to store data in a non-volatile manner;

a plurality of word lines, arranged corresponding to the respective rows of the memory cells, each formed of a first impurity region formed on a semiconductor substrate region and coupled to the resistance elements of the memory cells of a corresponding row;

a plurality of dummy cells, arranged in alignment with the memory cells in at least one of a row direction and a column direction, each including a variable resistance element being the same in number as each memory cell and suppressing means for preventing a current flow between a corresponding resistance element and the semiconductor substrate region, said semiconductor substrate region being coupled in common to the memory cells and the dummy cells.

4. The non-volatile semiconductor memory device according to claim 3, wherein the dummy cells are arranged in the row direction, and the suppressing means of each dummy cell comprises a high resistor of a high resistance provided between the corresponding resistance element and the semiconductor substrate region, said high resistance being higher than a resistance between the variable resistance element and the substrate region of each memory cell.

5. The non-volatile semiconductor memory device according to claim 3, wherein said preventing means comprises a second impurity region formed on said semiconductor substrate region and coupled to the corresponding resistance element, said second impurity region being opposite in conductivity type to said semiconductor substrate region and fixed to a bias potential for preventing the current flow between the corresponding resistance element and the semiconductor substrate region.

7. The non-volatile semiconductor memory device according to claim 3, wherein said variable resistance element includes a phase change element having a resistance value changing according to a crystalline state thereof.

10. The non-volatile semiconductor memory device according to claim 5, wherein

the dummy cells comprises cells arranged in alignment in a column direction in at least two columns;

said non-volatile semiconductor memory device further comprises a substrate shunting line arranged extending in a column direction and electrically connected to a substrate region for forming the memory cells at intervals covering a plurality of the memory cells arranged in the row direction in a region between the columns of the dummy cells.

6. A non-volatile semiconductor memory device comprising:

a plurality of memory cells, arranged in rows and columns, each including a variable resistance element having a resistance value set in accordance with stored data to store data in a non-volatile manner;

a plurality of word lines, arranged corresponding to the respective rows of the memory cells, each formed of a first impurity region formed on a semiconductor substrate region and coupled to the resistance elements of the memory cells of a corresponding row;

a plurality of dummy cells, arranged adjacently to memory cells, each including a variable resistance element being the same in number as each memory cell,

each memory cell further comprising a transistor switch having said first impurity region as a control electrode and selectively made conductive, in accordance with a signal potential on a corresponding word line, to electrically couple the resistance element to said semiconductor substrate region,

said plurality of dummy cells comprising dummy cells arranged in a line in alignment along the row direction, and

a substrate shunting line arranged along and adjacent to a row of the dummy cells arranged in a line, and electrically connected to said semiconductor substrate region of the dummy cells arranged in a line at an interval covering a plurality of the dummy cells.

8. The non-volatile semiconductor memory device according to claim 6, further comprising a word line shunting line, arranged extending in the row direction and corresponding to each memory cell row, and connected to the first impurity region of a corresponding row at an interval covering a plurality of the memory cells arranged in the row direction, said word line shunting line and said substrate shunting line formed separately and individually on a same interconnection layer.

9. The non-volatile semiconductor memory device according to claim 6, wherein said plurality of dummy cells comprises first dummy cells arranged in a line in alignment along a row direction, and second dummy cells arranged in a line in alignment along a column direction, and

the memory cells are arranged in alignment with the first and second dummy cells, and the first and second dummy cells are arranged in an array of the memory cells so as to be sandwiched by the memory cells.

11. A non-volatile memory device comprising:

a plurality of memory cells, arranged in rows and columns, each including (1) a phase change element having a crystalline state changing according to stored data, (2) a heater element coupled to said phase change element, for heating said phase change element and (3) a heat blocking layer formed at a region in at least one of a) a region between said heater element and a semiconductor substrate region and b) a region between said phase change element and a data transfer line, for suppressing heat from propagating from said heater elements; and

a plurality of bit lines, arranged corresponding to the columns of the memory cells, each connected to the memory cells on a corresponding column, and serving as said data transfer line, data stored in each memory cell determining an amount of current flow between a corresponding bit line and said semiconductor substrate region through said heat blocking layer.