Capacitor layout orientation

• US 7,208,813 B2
• Filed: 09/01/2005
• Issued: 04/24/2007
• Est. Priority Date: 06/27/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Baggenstoss, Bill
• Primary Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US11/218,996
• Publication Number:
  US 20060011992A1
• Time in Patent Office: 600 Days
• Field of Search: 257/396, 257/296, 257/68, 257/71, 257/300, 257/532
• US Class Current: 257/532
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto

Abstract

The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or other integrated circuit device. The capacitive memory elements may have a generally oblong shape and may be capacitive elements. The capacitive memory elements may be disposed in a slanted orientation. The capacitive memory elements may be disposed in a non-orthogonal orientation. The capacitive memory elements may be disposed so that an axis through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate. The axis may not be generally perpendicular with an orthogonal edge of the substrate. The plurality of capacitive memory elements may be arranged in a first row and a second row so that an axis through one of the plurality of capacitive memory elements located in the first row does not form an axis of any capacitive memory element in the second row.

Claims

1. An electronic device, comprising:

a processor adapted to executed instructions;

a storage device adapted to store instructions to be executed by the processor;

a user input device adapted to receive data for use by the processor from a user;

a display device adapted to produce an image for viewing by a user based on instructions executed by the processor; and

a memory device that receives information stored on the storage device, the memory device comprising;

a substrate; and

a plurality of capacitive memory elements disposed on the substrate so that an axis that runs longitudinally through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate, each of the plurality of capacitive memory elements comprising an outer sidewall and an inner sidewall, wherein the inner sidewall defines a generally convex volume.

2. The electronic device set forth in claim 1 wherein the axis is not generally perpendicular with an orthogonal edge of the substrate.

3. The electronic device set forth in claim 1 wherein each of the plurality of capacitive memory elements is generally oblong in shape.

4. The electronic device set forth in claim 3, wherein each of the plurality of capacitive memory elements is generally elliptical.

5. The electronic device set forth in claim 1 wherein each of the plurality of capacitive memory elements is slanted with respect to the edge of the substrate.

6. An electronic device, comprising:

a processor adapted to executed instructions;

a storage device adapted to store instructions to be executed by the processor;

a user input device adapted to receive data for use by the processor from a user;

a display device adapted to produce an image for viewing by a user based on instructions executed by the processor; and

a memory device that receives information stored on the storage device, the memory device comprising;

a plurality of capacitive memory elements arranged in a first row and a second row so that an axis through one of the plurality of capacitive memory elements located in the first row does not form an axis of any capacitive memory element in the second row.

7. The electronic device set forth in claim 6 wherein the plurality of capacitive memory elements is disposed on a substrate.

8. The electronic device set forth in claim 7 wherein the axis is not generally parallel with an edge of the substrate.

9. The electronic device set forth in claim 8 wherein the axis is not generally perpendicular with an orthogonal edge of the substrate.

10. The electronic device set forth in claim 6 wherein each of the plurality of capacitive memory elements is slanted with respect to the edge of the substrate.

11. The electronic device set forth in claim 6 wherein each of the plurality of capacitive memory elements is generally oblong in shape.

12. The electronic device set forth in claim 11, wherein each of the plurality of capacitive memory elements is generally elliptical.

13. The electronic device set forth in claim 6 wherein the axis is a longitudinal axis.