Semiconductor device

• US 7,208,844 B2
• Filed: 01/30/2004
• Issued: 04/24/2007
• Est. Priority Date: 10/31/2003
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Andoh, Seiji
• Primary Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US10/766,938
• Publication Number:
  US 20050093179A1
• Time in Patent Office: 1,180 Days
• Field of Search: 257/787, 257/678, 257/777
• US Class Current: 257/787
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor device including a substrate having a main surface including a first area, a second area surrounding the first area, and a third area surrounding the second area; a first insulating protective film that is provided in the first area and formed in a shape having no angles; a second insulating protective film provided in the third area; a semiconductor chip that is provided on the first insulating protective film and has a bottom surface facing to the first insulating protective film; and a sealing resin covering the semiconductor chip, wherein the bottom surface of the semiconductor chip covers the first area.

Claims

1. A semiconductor device comprising:

a substrate having a main surface including a first area, a second area surrounding the first area, and a third area surrounding the second area;

a first insulating protective film that is provided on the first area and formed in a shape having no angles;

a second insulating protective film provided on the third area;

a die bonding layer formed on the first insulating protective film and the second area of the substrate;

a semiconductor chip that is provided on the die bonding layer and has a bottom surface facing the die bonding layer; and

a sealing resin covering the semiconductor chip,

wherein the bottom surface of the semiconductor chip covers the first area and a part of the second area.

2. The semiconductor device according to claim 1, wherein the semiconductor has a first rectangular shape, the first area has a second rectangular shape that is smaller than the first rectangular shape and the second area has a predetermined width.

3. The semiconductor device according to claim 1, wherein the substrate has a plurality of interconnections locating from the first area to the third area through the second area.

4. The semiconductor device according to claim 3, wherein the substrate further has a plurality of bonding pads connected to the interconnections.

5. The semiconductor device according to claim 4, wherein the bonding pads are located on the third area.

6. The semiconductor device according to claim 3, wherein the substrate further has a plurality of through holes connected to the interconnections.

7. The semiconductor device according to claim 6, wherein the through holes are located on the first area.

8. The semiconductor device according to claim 1, wherein the substrate has a back surface opposite to the main surface and wherein the substrate has a plurality of conductive terminals located on the back side of the substrate.

9. The semiconductor device according to claim 8, wherein the conductive terminals are solder balls.