Image-sensor signal processing circuit

• US 7,208,983 B2
• Filed: 05/28/2004
• Issued: 04/24/2007
• Est. Priority Date: 05/29/2003
• Status: Active Grant

• Current Assignee: Hitachi Display Devices Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Matsuura, Tatsuji, Imaizumi, Eiki, Anbo, Takanobu, Odaka, Teruaki, Sone, Yasuhiko
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/855,608
• Publication Number:
  US 20040239783A1
• Time in Patent Office: 1,061 Days
• Field of Search: 327/91, 327/93, 327/94, 327/96, 348/241, 348/255, 348/229.1, 348/257, 348/222.1, 341/122
• US Class Current: 327/94
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

By flexibly coping with both image sensors of a CCD sensor and a CMOS sensor without providing any external circuit, a signal processing is performed. In a sensor selecting switch provided in an image-sensor signal-processing circuit, first and fourth switches are turned on when the CMOS sensor is connected, and second and third switches are turned on when the CCD sensor is connected. The sensor selecting switch is controlled by a control signal generated in a control circuit, based on sensor selection data which is stored in a register and which is data for selecting the CCD or CMOS sensor. By so doing, even if polarity of an output signal of the image sensor is reversed, a normal signal is inputted to both inputs of the CDS amplifier, whereby it is possible to flexibly cope with both of the CCD and CMOS sensors.

Claims

1. A semiconductor integrated circuit device, comprising:

a black-level sample/hold amplifier sampling and holding a black-level signal outputted from either of a first or second image sensor;

a sensor selecting section selecting, based on a selection control signal, each output destination of the pixel signal outputted from either of said first or second image sensor and of the black-level signal outputted from said black-level sample/hold amplifier;

a first amplifying portion sampling/holding the black-level signal and the pixel signal, and amplifying the black-level signal and the pixel signal;

a second amplifying portion amplifying the black-level signal and the pixel signal outputted from said first amplifying portion; and

an A/D converter converting, to a digital signal, the black-level signal and the pixel signal outputted from said second amplifier,

wherein said sensor selecting section selecting a first line as the output destination of the black-level signal and a second line as the output destination of the pixel signal during coupled to the first image sensor, or selecting the first line as the output destination of the pixel signal and the second line as the output destination of the black-level signal pixel signal during coupled to the second image sensor,

wherein the black-level signal outputted from the first image sensor is smaller than the pixel level outputted from the first image sensor, and the black-level signal outputted from the second image sensor is larger than the pixel level outputted from the second image sensor.

2. The semiconductor integrated circuit device according to claim 1, further comprising:

a sensor selecting register for storing sensor selection data,

wherein the selection control signal is generated based on the sensor selection data set in the sensor selecting register.

3. The semiconductor integrated circuit device according to claim 1,

wherein said first image sensor is a CMOS sensor and said second image sensor is a CCD sensor, and the sensor selection data set in said sensor selecting register corresponds to each of output waveforms of the CMOS sensor at the time of double sampling, the CCD sensor, and the CMOS sensor at the time of single sampling.

4. The semiconductor integrated circuit device according to claim 1,

wherein said sensor selecting section is provided at a former or latter stage of said first amplifying portion or at a former stage of said A/D converter.

5. The semiconductor integrated circuit device according to claim 2, further comprising:

a first bias switch which supplies a bias voltage,

wherein said first bias switch supplies a bias voltage to said black-level sampling/hold amplifier when the black-level signal outputted from either of said first or second image sensor is inputted to said black-level sample/hold amplifier in a pre-blank period.

6. The semiconductor integrated circuit device according to claim 5,

wherein said first bias switch selects based on the sensor selection data set in said sensor selecting register, a first bias voltage outputted at the time of selecting said second image sensor or a second bias voltage outputted at the time of selecting said first image sensor, and outputs the selected bias voltage.

7. The semiconductor integrated circuit device according to claim 1, further comprising:

a bias amplifier amplifying a bias voltage; and

a second bias switch supplying, to said black-level sampling/hold amplifier, the bias voltage outputted from said bias amplifier when the black-level signal outputted from either of said first or second image sensor is inputted to said black-level sample/hold amplifier in a pre-blank period, and

said bias amplifier biases said black-level sample/hold amplifier so that an output of said black-level sample/hold amplifier becomes almost equal to the bias voltage.

8. The semiconductor integrated circuit device according to claim 7, further comprising:

a third bias switch provided for;

selecting, based on the data set in said sensor selecting register, a first bias voltage outputted at the time of selecting said first image sensor or a second bias voltage outputted at the time of selecting said second image sensor; and

outputting the selected bias voltage to said bias amplifier.

9. The semiconductor integrated circuit device according to claim 1,

wherein at least two different bias voltages are inputted to said black-level sample/hold amplifier, and

said black-level sample/hold amplifier selects any one of said at least two bias voltages based on the black-level signal outputted from either of said first or second image sensor and supplies the selected bias voltage.

10. The semiconductor integrated circuit device according to claim 1,

wherein said first amplifying portion comprises:

a first sampling capacity element sampling a black-level sample/hold amplifier output signal of the black-level signal outputted from either of said first or second image sensor;

a second sampling capacity element sampling the pixel signal outputted from either of said first or second image sensor;

a signal amplifying portion sampling a difference between the black-level sample/hold amplifier output signal and the pixel signal; and

first and second feedback capacity elements coupled between an input and an output of said signal amplifying portion,

wherein when the black-level sample/hold amplifier output signal and the pixel signal are sampled to said first and second sampling capacity elements, a predetermined bias voltage is inputted to the input of said first amplifying portion and bias voltages are applied to said first and second feedback capacity elements.

11. The semiconductor integrated circuit device according to claim 1,

wherein said first amplifying portion comprises:

a first sampling capacity element sampling a black-level sample/hold amplifier output signal of the black-level signal outputted from either of said first or second image sensor;

a second sampling capacity element sampling the pixel signal outputted from either of said first or second image sensor;

a signal amplifier portion amplifying a difference between the black-level sample/hold amplifier output signal and the pixel signal; and

first and second feedback capacity elements coupled between an input and an output of said signal amplifying portion,

wherein when the black-level sample/hold amplifier output signal and the pixel signal are sampled to said first and second sampling capacity elements, at least two bias voltages are supplied to the input of said first amplifying portion,

one predetermined bias voltage is selected from said at least two bias voltages depending on selection of said first or second image sensor, and

bias voltages are applied to said first and second feedback capacity elements.

12. The semiconductor integrated circuit device comprising:

a sensor selecting section selecting, based on a sensor selection data, a first state in which a black-level signal is transmitted to a second line during coupling to a CCD sensor, or a second state in which a pixel signal is transmitted to the first line and a black-level signal is transmitted to the second line during coupling to a CMOS sensor;

a first amplifying portion sampling/holding the black-level signal and the pixel signal outputted from either of the CCD sensor or CMOS senors, and amplifying the black-level signal and the pixel signal outputted from either of the CCD sensor or CMOS sensor; and

an A/D converter converting, to a digital signal, the black-level signal and the pixel signal outputted from said first amplifying portion;

wherein the pixel signal outputted from the CCD sensor is smaller than the black-level signal outputted from the CCD sensor,

wherein the pixel signal outputted from the CMOS sensor is larger than the black-level signal outputted from the CMOS sensor.

13. The semiconductor integrated circuit device according to claim 12,

wherein the first line and second line are coupled to an input of the first amplifying portion, or the first line and second line are coupled to an input of the A/D converter.

14. The semiconductor integrated circuit device comprising:

a sensor selecting section selecting, based on a sensor selection data, a first state in which a black-level signal is transmitted to a first line and a pixel signal is transmitted to a second line during coupling to a CCD sensor, or a second state in which a pixel signal is transmitted to the first line and a black-level signal is transmitted to the second line during coupling to a CMOS sensor;

a first amplifying portion sampling/holding the black-level signal and the pixel signal outputted from either of the CCD sensor or CMOS sensor, and amplifying the black-level signal and the pixel signal outputted from either of the CCD sensor or CMOS sensor; and

an A/D converter converting, to a digital signal, the black-level signal and the pixel signal outputted from said first amplifying portion;

wherein the pixel signal outputted from the CCD sensor is smaller than the black-level signal outputted from the CCD sensor,

wherein the pixel signal outputted from the CMOS sensor is larger than the black-level signal outputted from the CMOS sensor;

a second amplifying portion amplifying the black-level signal and the pixel signal outputted from said first amplifying portion,

wherein the first line and second line are coupled to a input of the second amplifying portion.

15. The semiconductor integrated circuit device comprising:

a sensor selecting section selecting, based on a sensor selection data, a first state in which a black-level signal is transmitted to a first line and a pixel signal is transmitted to a second line during coupling to a CCD sensor, or a second state in which a pixel signal is transmitted to the first line and a black-level signal is transmitted to the second line during coupling to a CMOS sensor;

a first amplifying portion sampling/holding the black-level signal and the pixel signal outputted from either of the CCD sensor or CMOS sensor, and amplifying the black-level signal and the pixel signal outputted from either of the CCD sensor or CMOS sensor; and

an A/D converter converting, to a digital signal, the black-level signal and the pixel signal outputted from said first amplifying portion;

wherein the pixel signal outputted from the CCD sensor is smaller than the black-level signal outputted from the CCD sensor,

wherein the pixel signal outputted from the CMOS sensor is larger than the black-level signal outputted from the CMOS sensor;

wherein the sensor selection data set in said sensor selecting register corresponds to each of output waveforms of the CMOS sensor at the time of double sampling, the CCD sensor, and the CMOS sensor at the time of single sampling.