CMOS driver with minimum shoot-through current

• US 7,208,984 B1
• Filed: 07/15/2004
• Issued: 04/24/2007
• Est. Priority Date: 07/15/2004
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Petrofsky, Joseph G.
• Primary Examiner(s): Callahan; Timothy P.
• Assistant Examiner(s): Nguyen; Hiep
• Application Number:
  US10/891,108
• Time in Patent Office: 1,013 Days
• Field of Search: None
• US Class Current: 327/108
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356165 using additional transistors in the feedback circuit

Abstract

A CMOS driver with minimum shoot-through current is disclosed. The potential for shoot-through current may be eliminated or reduced with a break-before-make circuit driving an output stage. The break-before-make circuit may include a first logic element followed by a first inverter and a second logic element followed by a second inverter. The inverters may be cross-coupled to one another and/or the internal transistors may be configured with different strengths. The logic elements may be configured to eliminate or reduce potential shoot-through current paths, and the signal inputs may be controlled within a certain voltage range.

Claims

1. A break-before-make circuit, comprising:

a first logic element having an enabled state and a disabled state, the first logic element further having an output, and being configured to invert a signal input and provide the inverted signal input to its output in the enabled state, the first logic element further being configured to float its output in the disabled state when the signal input transitions to a first logic state;

a second logic element having an enabled state and a disabled state, the second logic element further having an output, and being configured to invert a signal input and provide the inverted signal input to its output in the enabled state, the second logic element further being configured to float its output in the disabled state when the signal input transitions to a second logic state, the second logic state having a higher voltage than the first logic state;

a first inverter having an input coupled to the output of the first logic element, and an output, the state of the second logic element being responsive to the first inverter output; and

a second inverter having an input coupled to the output of the second logic element, and an output, the state of the first logic element being a responsive to the second inverter output.

2. The break-before-make circuit of claim 1 wherein the first logic element is further configured to force its output to the first logic state when the signal input is in the second logic state when the first logic element is in the disabled state, and wherein the second logic element is further configured to force its output to the second logic state when the signal input is in the first logic state and the second logic element is in the disabled state.

3. The break-before-make circuit of claim 1 wherein the first logic element is enabled when the second inverter output is in the first logic state and disabled when the second inverter output is in the second logic state, and wherein the second logic element is enabled when the first inverter output is in the second logic state and disabled when the first inverter output is in the first logic state.

4. The break-before-make circuit of claim 1 wherein the first and second inverters have separate outputs, the first inverter being configured for a connection to a power supply return through the output of the second inverter, and the second inverter being configured for a connection to a power supply through the output of the first inverter.

5. The break-before-make circuit of claim 1 wherein the first inverter further comprises a series coupled PMOS and NMOS transistor configured to be coupled between a power supply and a power supply return, and wherein the second inverter further comprises a series coupled PMOS and NMOS transistor configured to be coupled between a power supply and a power supply return.

6. The break-before-make circuit of claim 5 wherein the PMOS transistor in the first inverter is stronger than the NMOS transistor in the first inverter, and wherein the NMOS transistor in the second inverter is stronger than the PMOS transistor in the second inverter.

7. The break-before-make circuit of claim 1 wherein the first and second logic elements each comprises a plurality of transistors coupled in series, and wherein the signal input and the second inverter output are used in the first logic element only to control the series transistors therein, and wherein the signal input and the first inverter output are used in the second logic element only to control the series transistors therein.

8. The break-before-make circuit of claim 7 wherein the transistors in the first logic element comprise a first PMOS transistor configured to be coupled to a power supply, a first NMOS transistor configured to be coupled to a power supply return, and a second PMOS transistor coupled between the first PMOS transistor and the first NMOS transistor, the first PMOS transistor and the first NMOS transistor being configured to receive the signal input, the second inverter output being coupled to the second PMOS transistor, and the output of the first logic element being taken between the second PMOS transistor and the first NMOS transistor, and wherein the second logic element comprise a third PMOS transistor configured to be coupled to the power supply, a second NMOS transistor configured to be coupled to the power supply return, and a third NMOS transistor coupled between the third PMOS transistor and the second NMOS transistor, the third PMOS transistor and the second NMOS transistor being configured to receive the signal input, the first inverter output being coupled to the third NMOS transistor, and the output of the second logic element being taken between the third PMOS transistor and the third NMOS transistor.

9. The break-before-make circuit of claim 8 wherein the first and second inverters each comprises a PMOS transistor and a NMOS transistor connected in series, the PMOS transistor in the first inverter being configured to be coupled to the power supply, the NMOS transistor in the first inverter being coupled to the second inverter output, the PMOS transistor in the second inverter being coupled to the first inverter output and the NMOS transistor in the second inverter being configured to be coupled to the power supply return.

10. The break-before-make circuit of claim 9 wherein the PMOS transistor in the first inverter is stronger than the NMOS transistor in the first inverter, and the NMOS transistor in the second inverter is stronger than the PMOS transistor in the second inverter.

11. A break-before-make circuit, comprising:

first and second inverters each having an input and output;

a first logic element comprising a first NMOS transistor configured to be coupled to a power supply return, and first and second PMOS transistors coupled in series and configured to be coupled between a power supply and the first NMOS transistor, the first PMOS transistor and the first NMOS transistor being configured to receive a signal input, the second inverter output being coupled to the second PMOS transistor, and the input to the first inverter being taken from between the first NMOS transistor and the series combination of the first and second PMOS transistors, and wherein the first logic element does not include a NMOS transistor which is coupled in parallel with the first NMOS transistor and controlled by the second inverter output; and

a second logic element comprising a third PMOS transistor configured to be coupled to the power supply, and second and third NMOS transistors coupled in series and configured to be coupled between the power supply return and the third PMOS transistor, the third PMOS transistor and the second NMOS transistor being configured to receive the signal input, the first inverter output being coupled to the third NMOS transistor, and the input to the second inverter being taken between the third PMOS transistor and the series combination of the second and third NMOS transistors, and wherein the second logic element does not include a PMOS transistor which is coupled in parallel with the third PMOS transistor and controlled by the first inverter output.

12. A break-before-make circuit, comprising:

first and second logic elements each having an enabled state and a disabled state, each of the first and second logic elements having an output, and being configured to invert a signal input and provide the inverted signal input to its respective output in the enabled state;

a first inverter having an input coupled to the output of the first logic element, and an output, wherein the state of the second logic element is responsive to the first inverter output; and

a second inverter having an input coupled to the output of the second logic element, and an output separate from the output of the first inverter, wherein the state of the first logic element is responsive to the second inverter output;

wherein the first inverter is configured to be connected to a power supply return through the output of the second inverter, and the second inverter is configured to be connected to a power supply through the output of the first inverter.

13. The break-before-make circuit of claim 12 wherein the first inverter further comprises a PMOS transistor configured to be coupled to a power supply, and wherein the second inverter further comprises a NMOS transistor configured to be coupled to a power supply return.

14. The break-before-make circuit of claim 13 wherein the PMOS transistor in the first inverter is stronger than the NMOS transistor in the first inverter, and wherein the NMOS transistor in the second inverter is stronger than the PMOS transistor in the second inverter.

15. The break-before-make circuit of claim 12 wherein the first logic element is further configured to float its output in the disabled state when the signal input transitions to a first logic state, and wherein the second logic element is further configured to float its output in the disabled state when the signal input transitions to a second logic state, the second logic state having a higher voltage than the first logic state.

16. The break-before-make circuit of claim 15 wherein the first logic element is further configured to force its output to the first logic state when the signal input is in the second logic state and the first logic element is in the disabled state, and wherein the second logic element is further configured to force its output to the second logic state when the signal input is in the first logic state and the second logic element is in the disabled state.

17. The break-before-make circuit of claim 15 wherein the first logic element is enabled when the second inverter output is in the first logic state and disabled when the second inverter output is in the second logic state, and wherein the second logic element is enabled when the first inverter output is in the second logic state and disabled when the first inverter output is in the first logic state.

18. The break-before-make circuit of claim 15 wherein the first and second logic elements each comprises a plurality of transistors coupled in series, and wherein the signal input and the second inverter output are used in the first logic element only to control the series transistors therein, and wherein the signal input and the first inverter output are used in the second logic element only to control the series transistors therein.

19. The break-before-make circuit of claim 18 wherein the transistors in the first logic element comprise a first PMOS transistor configured to be coupled to a power supply, a first NMOS transistor configured to be coupled to a power supply return, and a second PMOS transistor coupled between the first PMOS transistor and the first NMOS transistor, the first PMOS transistor and the first NMOS transistor being configured to receive the signal input, the second inverter output being coupled to the second PMOS transistor, and the output of the first logic element being taken between the second PMOS transistor and the first NMOS transistor, and wherein the second logic element comprise a third PMOS transistor configured to be coupled to the power supply, a second NMOS transistor configured to be coupled to the power supply return, and a third NMOS transistor coupled between the third PMOS transistor and the second NMOS transistor, the third PMOS transistor and the second NMOS transistor being configured to receive the signal input, the first inverter output being coupled to the third NMOS transistor, and the output of the second logic element being taken between the third PMOS transistor and the third NMOS transistor.

20. The break-before-make circuit of claim 19 wherein the first inverter further comprises a PMOS transistor configured to be coupled to a power supply, and wherein the second inverter further comprises a NMOS transistor configured to be coupled to a power supply return.

21. The break-before-make circuit of claim 19 wherein the PMOS transistor in the first inverter is stronger than the NMOS transistor in the first inverter, and wherein the NMOS transistor in the second inverter is stronger than the PMOS transistor in the second inverter.

22. A break-before-make circuit, comprising:

first and second logic elements configured to receive a common input that varies between a first and second state, the first logic element having an output coupled to a second input of the second logic element and the second logic element having an output coupled to a second input of the first logic element such that, when the common input transitions from the first state to the second state, the first logic element floats its output until it receives at its second input a transition in the output from the second logic element, and when the common input transitions from the second state to the first state, the second logic element floats its output until it receives at its second input a transition in the output from the first logic element.

23. The break-before-make circuit of claim 22 further comprising a first inverter configured to couple the output from the first logic element to the second input of the second logic element, and a second inverter configured to couple the output from the second logic element to the second input of the first logic element.

24. The break-before-make circuit of claim 23 wherein the first inverter comprises an output coupled to the second inverter and the second inverter includes an output coupled to the first inverter.

25. The break-before-make circuit of claim 24 wherein each of the first and second inverters includes a PMOS coupled in series with a NMOS transistor, and wherein the output of the first inverter is coupled to the PMOS transistor in the second inverter and the output of the second inverter is coupled to the NMOS transistor in the first inverter.

26. The break-before-make circuit of claim 25 wherein the PMOS transistor in the first inverter is stronger than the NMOS transistor in the first inverter, and wherein the NMOS transistor in the second inverter is stronger than the PMOS transistor in the second inverter.

27. The break-before-make circuit of claim 22 further comprising an output driver responsive to the outputs of the first and second logic elements.

28. The break-before-make circuit of claim 27 wherein the output driver comprises a CMOS driver.

29. The break-before-make circuit of claim 27 further comprising a first inverter configured to couple the output from the first logic element to the output driver, and a second inverter configured to couple the output from the second logic element to the output driver.

30. The break-before-make circuit of claim 29 wherein the first inverter is further configured to couple the output from the first logic element to the second input of the second logic element, and the second inverter is further configured to couple the output from the second logic element to the second input of the first logic element.