Bias circuit for high-swing cascode current mirrors

• US 7,208,998 B2
• Filed: 04/12/2005
• Issued: 04/24/2007
• Est. Priority Date: 04/12/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Abel, Christopher J.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US11/103,813
• Publication Number:
  US 20060226893A1
• Time in Patent Office: 742 Days
• Field of Search: None
• US Class Current: 327/538
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A bias circuit for providing at least first and second bias signals for biasing a cascode current source and/or a cascode current sink includes a resistive element and first, second and third transistors, each transistor having first and second source/drain terminals and a gate terminal. The first source/drain terminal of the first transistor is coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal. A first end of the first resistive element is coupled to the second source/drain terminal of the first transistor. The gate terminal of the second transistor is coupled to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor. The first source/drain terminal of the third transistor is coupled to the second source/drain terminal of the second transistor, the second source/drain terminal of the third transistor is coupled to a second end of the first resistive element, and the gate terminal of the third transistor is coupled to the first source/drain terminal of the second transistor.

Claims

1. A bias circuit for providing at least first and second bias signals for biasing at least one of a cascode current source and a cascode current sink, the bias circuit comprising:

a first transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal being coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal;

a first resistive element including first and second ends, the first end of the first resistive element being coupled to the second source/drain terminal of the first transistor;

a second transistor including first and second source/drain terminals and a gate terminal, the gate terminal of the second transistor being connected to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor;

a third transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal of the third transistor being coupled to the second source/drain terminal of the second transistor, the second source/drain terminal of the third transistor being coupled to the second end of the first resistive element, and the gate terminal of the third transistor being coupled to the first source/drain terminal of the second transistor; and

a compensation circuit operative to subtract at least a portion of current flowing through the first resistive element, such that a net current flowing through the first resistive element is substantially a function of a resistance of a second resistive element which is ratio matched to a resistance of the first resistive element.

2. The circuit of claim 1, wherein each of the first, second and third transistors comprises an NMOS device.

3. The circuit of claim 1, wherein each of the first, second and third transistors comprises a PMOS device.

4. The circuit of claim 1, wherein a voltage across the first resistive element is substantially matched to a voltage across the first and second source/drain terminals of the third transistor.

5. The circuit of claim 1, wherein a voltage across the first resistive element is selected to be greater than or substantially equal to a worst-case minimum saturation voltage of the third transistor for a desired operating range of the bias circuit.

6. The circuit of claim 1, wherein the first transistor is substantially matched to the second transistor, and wherein the first and second reference currents are substantially equal to one another.

7. The circuit of claim 1, wherein the first and second reference currents are a provided by a reference generator comprising the second resistive element, the first and second reference currents being a function of the second resistive element, a ratio of the first and second resistive elements being substantially constant over at least one of process, voltage and temperature variations to which the bias circuit is subjected.

8. The circuit of claim 1, wherein the first and second reference currents are provided by a reference generator comprising the second resistive element, the first and second reference currents being inversely proportional to the second resistive element, a ratio of the first and second resistive elements being substantially constant over at least one of process, voltage and temperature variations to which the bias circuit is subjected.

9. A bias circuit for providing at least first and second bias signals for biasing at least one of a cascode current source and a cascode current sink, the bias circuit comprising:

a first transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal being coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal;

a first resistive element including first and second ends, the first end of the first resistive element being coupled to the second source/drain terminal of the first transistor;

a second transistor including first and second source/drain terminals and a gate terminal, the gate terminal of the second transistor being connected to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor;

a third transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal of the third transistor being coupled to the second source/drain terminal of the second transistor, the second source/drain terminal of the third transistor being coupled to the second end of the first resistive element, and the gate terminal of the third transistor being coupled to the first source/drain terminal of the second transistor;

a fourth transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal of the fourth transistor being coupled to the gate terminal of the fourth transistor, and the second source/drain terminal of the fourth transistor being coupled to the second end of the first resistive element; and

a fifth transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal of the fifth transistor being coupled to the first end of the first resistive element, the second source/drain terminal of the fifth transistor being coupled to the second end of the first resistive element, and the gate terminal of the fifth transistor being coupled to the gate terminal of the fourth transistor.

10. The circuit of claim 9, wherein each of the fourth and fifth transistors comprises an NMOS device.

11. The circuit of claim 9, wherein the first and second reference currents are substantially selectively controlled as a function of a resistance of an off-chip resistor, and the first source/drain terminal of the fourth transistor receives a third reference current which is subtracted from the first reference current, the third reference current being a function of both the resistance of the off-chip resistor and a resistance of the first resistive element, such that a current flowing through the first resistive element generates a voltage drop across the first resistive element that is substantially independent of at least one of process, voltage and temperature variations to which the bias circuit is subjected.

12. The circuit of claim 9, wherein the first and second reference currents are substantially independent of a resistance of the first resistive element, and the first source/drain terminal of the fourth transistor receives a third reference current which is substantially equal to a difference between the first reference current and a fourth reference current which is substantially inversely proportional to the resistance of the first resistive element, such that a current flowing through the first resistive element generates a voltage drop across the first resistive element that is substantially independent of at least one of process, voltage and temperature variations to which the bias circuit is subjected.

13. The circuit of claim 12, wherein the first and second reference currents are selectively controlled as a function of a resistance of an off-chip resistor.

14. An integrated circuit including at least one bias circuit for providing at least first and second bias signals for biasing at least one of a cascode current source and a cascode current sink, the at least one bias circuit comprising:

a first transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal being coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal;

a first resistive element including first and second ends, the first end of the first resistive element being coupled to the second source/drain terminal of the first transistor;

a second transistor including first and second source/drain terminals and a gate terminal, the gate terminal of the second transistor being connected to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor;

a third transistor including first and second source/drain terminals and a gate terminal, the first source/drain terminal of the third transistor being coupled to the second source/drain terminal of the second transistor, the second source/drain terminal of the third transistor being coupled to the second end of the first resistive element, and the gate terminal of the third transistor being coupled to the first source/drain terminal of the second transistor; and

a compensation circuit operative to subtract at least a portion of current flowing through the first resistive element, such that a net current flowing through the first resistive element is substantially a function of a resistance of a second resistive element which is ratio matched to a resistance of the first resistive element.

15. The integrated circuit of claim 14, wherein a voltage across the first resistive element is substantially matched to a voltage across the first and second source/drain terminals of the third transistor.

16. The integrated circuit of claim 14, wherein a voltage across the first resistive element is selected to be greater than or substantially equal to a worst-case minimum saturation voltage of the third transistor for a desired operating range of the bias circuit.

17. The integrated circuit of claim 14, wherein the first and second reference currents are a provided by a reference generator comprising the second resistive element, the first and second reference currents being a function of the second resistive element, a ratio of the first and second resistive elements being substantially constant over at least one of process, voltage and temperature variations to which the bias circuit is subjected.

18. The integrated circuit of claim 14, wherein the first and second reference currents are a provided by a reference generator comprising the second resistive element, the first and second reference currents being inversely proportional to the second resistive element, a ratio of the first and second resistive elements being substantially constant over at least one of process, voltage and temperature variations to which the bias circuit is subjected.