Analog to digital converter elements and methods for using such

• US 7,209,068 B1
• Filed: 02/03/2006
• Issued: 04/24/2007
• Est. Priority Date: 02/03/2006
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bailey, James A., Chen, Mingdeng, Mortezapour, Siamak
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US11/347,345
• Time in Patent Office: 445 Days
• Field of Search: 341/155, 341/161
• US Class Current: 341/161
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence

Abstract

Various systems and methods for converting a signal from the analog domain to the digital domain are disclosed herein. As one example, an analog-to-digital converter is disclosed that includes two pipelined analog-to-digital converter stages. The first analog-to-digital converter stage provides an encoded word output and the second analog-to-digital converter stage provides an unencoded word output. A summation device is provided to aggregate the encoded word output with the unencoded word output.

Claims

1. An analog-to-digital converter, the analog-to-digital converter comprising:

a preceding analog-to-digital converter stage, wherein the preceding analog-to-digital converter stage is a 2.3 bit analog to digital converter stage, and wherein the preceding analog-to-digital converter stage provides an encoded word output and an analog residue output; and

a subsequent analog-to-digital converter stage, wherein the subsequent analog-to-digital converter stage provides an unencoded word output, and wherein the subsequent analog-to-digital converter stage is electrically coupled to the analog residue output of the preceding analog-to-digital converter stage.

2. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter further comprises:

a summation device, wherein the summation device receives the encoded word output and the unencoded word output, and wherein the summation device is operable to aggregate the unencoded word output and the encoded word output.

3. The analog-to-digital converter of claim 1, wherein the unencoded word output is representative of the analog residue output provided by the preceding analog-to-digital converter stage.

4. The analog-to-digital converter of claim 1, wherein the encoded word output is a four bit encoded word output, and wherein the unencoded word output is a two bit unencoded word output.

5. The analog-to-digital converter of claim 4, wherein the 2.3 bit analog-to-digital converter stage is a preceding 2.3 bit analog-to-digital converter stage, wherein the preceding 2.3 bit analog-to-digital converter stage provides a first analog residue output, wherein the four bit encoded word output is a first four bit encoded word output, and wherein the analog-to-digital converter further comprises:

a subsequent 2.3 bit analog-to-digital converter stage, wherein the subsequent 2.3 bit analog-to-digital converter stage provides a second four bit encoded word output, and wherein the subsequent 2.3 bit analog-to-digital converter stage provides a second analog residue output; and

wherein the second analog residue output is provided to the preceding analog-to-digital converter stage as an input.

6. The analog-to-digital converter of claim 5, wherein the analog-to-digital converter further comprises:

a summation device, wherein the summation device receives the first four bit encoded word output, the second four bit encoded word output and the two bit unencoded word output, wherein the summation device is operable to shift the second four bit encoded word output left two positions to create a shifted four bit encoded word output, and wherein the summation device is operable to aggregate the first four bit encoded word output, the shifted four bit encoded word output and the two bit unencoded word output.

7. The analog-to-digital converter of claim 4, wherein the 2.3 bit analog-to-digital converter stage provides a first analog residue output, wherein the two bit unencoded word output is a first unencoded word output, and wherein the analog-to-digital converter further comprises:

a 2.8 bit analog-to-digital converter stage, wherein the 2.8 bit analog-to-digital converter stage provides a second two bit unencoded word output, wherein the 2.8 bit analog-to-digital converter stage provides a second analog residue output, and wherein the 2.8 bit analog-to-digital converter stage receives the first analog residue output as an input; and

wherein the second analog residue output is provided to the second analog-to-digital converter stage as an input.

8. The analog-to-digital converter of claim 7, wherein the analog-to-digital converter further comprises:

a summation device, wherein the summation device receives the four bit encoded word output, the first two bit unencoded word output and the second two bit unencoded word output; and

wherein the summation device is operable to;

shift the four bit encoded word output left two positions;

shift the first two bit unencoded word output left two positions; and

aggregate the shifted four bit encoded word output, the shifted first two bit unencoded word output and the second two bit unencoded word output.

9. The analog-to-digital converter of claim 4, wherein the four bit encoded data word represents five levels, and wherein the four bit encoded data word is encoded with the following codes representing each of the five levels:

first level ‘

0000’

;

second level ‘

0011’

;

third level ‘

0110’

;

fourth level ‘

1001’

; and

fifth level ‘

11100’

.

10. The analog-to-digital converter of claim 4, wherein the 2.3 bit analog-to-digital converter stage includes:

four comparators; and

an encoder.

11. The analog-to-digital converter of claim 1, wherein the preceding analog-to-digital converter stage includes:

a 2.3 bit analog-to-digital converter, wherein the 2.3 bit analog-to-digital converter is electrically coupled to an analog voltage input, wherein the 2.3 bit analog-to-digital converter is operable to provide a raw data word representative of the analog voltage input less a residue, wherein the 2.3 bit analog-to-digital converter is operable to provide the encoded word output, and wherein the encoded word output is representative of the analog voltage input less the residue;

a digital-to-analog converter, wherein the digital-to-analog converter receives the raw data word as an input, and wherein the digital-to-analog converter is operable to provide a first analog output representative of the analog voltage input less the residue;

a summation device, wherein the summation device is configured to subtract the first analog output from the analog voltage input to form a pre-amplified analog residue output; and

an amplifier, wherein the amplifier is operable to receive and amplify the pre-amplified analog residue output to form the analog residue output.

12. A method for implementing an analog-to-digital converter, wherein the method comprises:

providing a preceding analog-to-digital converter stage, wherein the preceding analog-to-digital converter stage is a 2.3 bit analog-to-digital converter stage, and wherein the preceding analog-to-digital converter stage provides an encoded word output;

providing a subsequent analog-to-digital converter stage, wherein the subsequent analog-to-digital converter stage provides an unencoded word output;

providing a summation device;

electrically coupling a residue output of the preceding analog-to-digital converter stage to an input port of the subsequent analog-to-digital converter stage; and

adding the encoded word output with the unencoded word output in the summation device.

13. The method of claim 12, wherein the preceding analog-to-digital converter stage is a first 2.3 bit analog-to-digital converter stage, wherein the encoded output is a first encoded output, wherein the residue output is a first residue output, and wherein the method further comprises:

providing a second 2.3 bit analog-to-digital converter stage, wherein the second 2.3 bit analog-to-digital converter stage provides a second encoded word output;

electrically coupling a second residue output of the second 2.3 bit analog-to-digital converter stage to an input of the first 2.3 bit analog-to-digital converter stage;

shifting the second encoded data word left two positions; and

adding the first encoded word output, the second encoded word output and the unencoded word output in the summation device.

14. The method of claim 12, wherein the summation device is a first summation device, and wherein the preceding analog-to-digital converter stage includes:

a 2.3 bit analog-to-digital converter, wherein the 2.3 bit analog-to-digital converter is electrically coupled to an analog voltage input, wherein the 2.3 bit analog-to-digital converter is operable to provide a raw data word representative of the analog voltage input less a residue, wherein the 2.3 bit analog-to-digital converter is operable to provide the encoded word, and wherein the encoded word is representative of the analog voltage input less the residue;

a digital-to-analog converter, wherein the digital-to-analog converter receives the raw data word as an input, and wherein the digital-to-analog converter is operable to provide a first analog output representative of the analog voltage input less the residue;

a second summation device, wherein the second summation device is configured to subtract the first analog output from the analog voltage input to form an analog residue output; and

an amplifier, wherein the amplifier is operable to receive and amplify the analog residue output.

15. The method of claim 12, wherein the preceding analog-to-digital converter stage is a first 2.3 bit analog-to-digital converter stage, and wherein the subsequent analog-to-digital converter stage is selected from a group consisting of:

a three comparator analog-to-digital converter stage, and a six comparator analog-to-digital comparator stage.

16. A pipelined analog-to-digital converter, the pipelined analog-to-digital converter comprising:

a two bit, four comparator analog-to-digital converter stage, wherein the two bit, four comparator analog-to-digital converter stage provides an encoded word output representing five successive levels, and wherein the two bit, four comparator analog-to-digital converter stage provides an analog residue output; and

a two bit analog-to-digital converter stage, wherein the two bit analog-to-digital converter receives the analog residue output and provides a two bit unencoded word representative of the analog residue output.

17. The pipelined analog-to-digital converter of claim 16, wherein the pipelined analog-to-digital converter further comprises:

a summation device, wherein the summation device is operable to aggregate the encoded word output with the two bit unencoded word.

18. The pipelined analog-to-digital converter of claim 17, wherein the two bit, four comparator analog-to-digital converter stage is a preceding two bit, four comparator analog-to-digital converter stage, wherein the analog residue output is a first analog residue output, wherein the encoded word output is a first encoded word output, and wherein the pipelined analog-to-digital converter further comprises:

a subsequent two bit, four comparator analog-to-digital converter stage, wherein the subsequent two bit, four comparator analog-to-digital converter stage provides a second encoded word output representing five successive levels, and wherein the second two bit, four comparator analog-to-digital converter stage provides a second analog residue output; and

wherein the second analog residue input is provided to the preceding two bit, four comparator analog-to-digital converter stage, wherein the first encoded word output is representative of the second analog residue output less a residue, and wherein the first analog residue output is representative of the residue.

19. The pipelined analog-to-digital converter of claim 18, wherein the summation device is operable to:

receive the second encoded word;

shift the second encoded word left two positions; and

aggregate the first encoded word, the second encoded word and the two bit unencoded word.

20. The pipelined analog-to-digital converter of claim 16, wherein the encoded word is a four bit word encoded with the following codes representing the respective levels:

first level ‘

0000’

;

second level ‘

0011’

;

third level ‘

0110’

;

fourth level ‘

1001’

; and

fifth level ‘

1100’

.