Method and apparatus for asynchronous display of graphic images

• US 7,209,133 B2
• Filed: 02/07/2003
• Issued: 04/24/2007
• Est. Priority Date: 06/28/1996
• Status: Expired due to Fees

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA International Inc. (NVIDIA Corporation)
• Inventors: Eglit, Alexander J., Bril, Vlad, Kotha, Sridhar
• Primary Examiner(s): Lefkowitz; Sumati
• Assistant Examiner(s): Kumar; Srilakshmi K
• Application Number:
  US10/359,734
• Publication Number:
  US 20030227471A1
• Time in Patent Office: 1,537 Days
• Field of Search: 345/1.1, 345/3.1, 345/53, 345/208, 345/213, 345/531, 345/660, 348/497, 348/500, 348/537, 348/715, 341/61
• US Class Current: 345/213
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/008 Clock recovery

Abstract

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Claims

1. In a computer system, a display controller for controlling asynchronous output of a graphics data to at least one display device, said display controller comprising:

time base converter means for receiving graphics display data at a first rate, timing signals, and signals indicative of horizontal scan rate, said time base converter means for outputting the graphics display data at least one second asynchronous rate;

storage means coupled to said time base converter means for receiving and storing graphics display data at said at least one second asynchronous rate and outputting the graphics display data stored therein; and

interpolator means separate and downstream from said storage means and said time base converter means for upscaling the graphics display data to at least one graphics display resolution and outputting the graphics display data to a display device;

wherein said first rate and said at least one second asynchronous rate are different.

2. In a computer system, a display controller for controlling asynchronous output of a graphics data to at least one display device, said display controller comprising:

time base converter means for receiving graphics display data at a first rate, timing signals, and signals indicative of horizontal scan rate, said time base converter means for outputting the graphics display data at least one second asynchronous rate;

storage means separate and downstream from said time base converter means for receiving and storing graphics display data at said at least one second asynchronous rate and outputting the graphics display data stored therein;

interpolator means coupled to said storage means and said time base converter means for upscaling the graphics display data to at least one graphics display resolution and outputting the graphics display data to a display device;

horizontal Discrete Time Oscillator means coupled to said interpolator means and said time base converter means for receiving at least one predetermined value proportional to a horizontal scan parameter and for outputting to said interpolator a signal indicative of a horizontal phase value and outputting to said time base converter a carry out signal; and

vertical Discrete Time Oscillator means coupled to said storage means and said interpolator means for receiving a predetermined numerator value and a predetermined denominator value and for outputting a value proportional to vertical phase and a value indicating the end of a vertical scan;

wherein said first rate and said at least one second asynchronous rate are different.

3. The display controller of claim 2, wherein said time base converter means further comprises a storage means for storing a line of graphics display data and outputting the line of graphics display data asynchronously at said at least one second asynchronous rate.

4. The display controller of claim 3, wherein said time base converter means further repeats outputting the line of graphics display data stored in said storage means if a line generated at said first rate is still being output when a subsequent line at said at least one second asynchronous rate is ready to be output.

5. The display controller of claim 2, wherein said storage means further comprises a line buffer and at least two flip-flops for storing pixel values.

6. The display controller of claim 2, wherein said horizontal Discrete Time Oscillator means further receives a first predetermined value proportional to a horizontal scan line size and a second predetermined value proportional to a horizontal total size and for outputting to said interpolator a signal indicative of a horizontal phase value and outputting to said time base converter a carry out signal generated in proportion to a ratio between said first and second predetermined values.

7. A method of controlling output of graphics display data in a computer system, said method comprising:

receiving graphics display data at a first resolution,

converting from a first time base corresponding to the first resolution to at least one second time base for displaying data at least one second resolution,

storing display data in a storage device and controlling the output of display data from said storage device to an interpolator which is separate and downstream from said storage device,

receiving at least one horizontal size parameter and outputting a horizontal phase signal and a carry out signal,

receiving at least one vertical frequency parameter and outputting a vertical phase signal and a signal indicative of the end of a scan interval,

interpolating graphics display data received at the at least one second resolution, and

outputting graphics display data from the interpolator to at least one display device at the at least one second resolution;

wherein said first base and said at least one second time base are different.

8. The method of claim 7, wherein said step of receiving at least one horizontal size parameter further comprises receiving said at least one horizontal size parameter in a horizontal Discrete Time Oscillator and outputting a horizontal phase signal and a carry out signal from said horizontal Discrete Time Oscillator.

9. The method of claim 7, wherein said step of receiving at least one vertical frequency parameter further comprises receiving said at least one vertical frequency parameter in a vertical Discrete Time Oscillator and outputting a vertical phase signal and a signal indicative of the end of a scan interval from said vertical Discrete Time Oscillator.

10. A computer comprising:

a processor having core logic, primary and secondary memory, and at least one system bus,

at least one display coupled to said processor for displaying graphics and text output, and

a display controller coupled to said processor and said flat panel display for receiving graphics display data at a first resolution, controlling asynchronous output of graphics display data in at least one second resolution,

wherein said display controller further comprises;

time base converter means for receiving graphics display data at a first rate, timing signals, and signals indicative of horizontal scan rate and for outputting the graphics display data at least one second asynchronous rate;

storage means separate and downstream from said time base converter means for receiving and storing graphics display data at said at least one second asynchronous rate and outputting the graphics display data stored therein at said second asynchronous rate;

interpolator means coupled to said storage means and said time base converter means for receiving display data at said second asynchronous rate upscaling the graphics display data to at least one graphics display resolution;

horizontal Discrete Time Oscillator means coupled to said interpolator means and said time base converter means for receiving a predetermined value proportional to a horizontal scan line size and for outputting a value proportional to a horizontal phase to said interpolator; and

vertical Discrete Time Oscillator means coupled to said storage means and said interpolator means for receiving a predetermined numerator value and a predetermined denominator value and for outputting a value proportional to vertical phase and a value indicating the end of a vertical scan,

wherein said storage means further comprises a line buffer and at least two flip-flop elements for storing pixel values;

wherein said first rate and said at least one second asynchronous rate are different.

11. The computer of claim 10, wherein said control means further comprises at least one register means for storing a predetermined ratio corresponding to a present input resolution and a desired output resolution for the graphics display data.

12. The computer of claim 11, wherein said at least one display comprises a flat panel display having a fixed resolution.

13. The computer of claim 12, further comprising at least two displays wherein a first display comprises a flat panel display with a fixed resolution, and a second display comprises a fixed resolution CRT display.

14. The computer of claim 13, wherein said predetermined numerator received by said vertical Discrete Time Oscillator means is proportional to the vertical size of an LCD panel and said predetermined denominator received by said vertical Discrete Time Oscillator means is proportional to the vertical size of a CRT display.

15. The computer of claim 14, wherein said LCD panel is a fixed resolution LCD panel and said CRT display is a fixed resolution CRT projection display.

16. The computer of claim 15, wherein said LCD panel is a fixed resolution LCD panel and said CRT display is a fixed resolution projection display and the resolution of said fixed resolution CRT projection display is lower than the resolution of said fixed resolution LCD display.

17. In a computer system, a display controller for controlling asynchronous output of a graphics data to at least one display device, said display controller comprising:

a time base converter for receiving graphics display data at a first rate, timing signals, and signals indicative of horizontal scan rate, said time base converter for outputting the graphics display data at least one second asynchronous rate;

storage coupled to said time base converter for receiving and storing graphics display data at said at least one second asynchronous rate and outputting the graphics display data stored therein; and

an interpolator separate and downstream from said storage and said time base converter for upscaling the graphics display data to at least one graphics display resolution and outputting the graphics display data to a display device;

wherein said first rate and said at least one second asynchronous rate are different.