Transient detection circuit
First Claim
Patent Images
1. A transient detection circuit comprising:
- a filter circuit coupled to a first node and a second node, the filter circuit having an output; and
an inverter circuit having an input coupled to the output of the filter circuit, the inverter circuit having a voltage switch point that includes an at least substantially constant voltage offset from the first node, wherein the at least substantially constant voltage is generated using a resistor coupled between the first node and a p-MOS transistor and a sustantially constant current source coupled between the p-MOS transistor and the second node.
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Abstract
A transient detection circuit which may be used in an electrostatic discharge (ESD) clamp circuit. The transient detection circuit includes a filter circuit and an inverter circuit. The voltage switch point of the inverter circuit has a constant voltage offset from one of the nodes. When a filtered voltage level from the filter circuit crosses the voltage switch point of the inverter circuit (indicative of an ESD event), the inverter circuit provides a signal indicating an ESD event.
63 Citations
26 Claims
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1. A transient detection circuit comprising:
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a filter circuit coupled to a first node and a second node, the filter circuit having an output; and an inverter circuit having an input coupled to the output of the filter circuit, the inverter circuit having a voltage switch point that includes an at least substantially constant voltage offset from the first node, wherein the at least substantially constant voltage is generated using a resistor coupled between the first node and a p-MOS transistor and a sustantially constant current source coupled between the p-MOS transistor and the second node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17)
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11. A transient detection circuit comprising:
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a filter circuit coupled to a first node and a second node, the filter circuit having an output, wherein the first node is coupled to receive a first power supply voltage and the second node is coupled to receive a second power supply voltage, and wherein the first power supply voltage is ground and the second power supply voltage is a positive voltage; and an inverter circuit having an input coupled to the output of the filter circuit, the inverter circuit having a voltage switch point that includes an at least substantially constant voltage offset from the first node, wherein the at least substantially constant voltage offset is generated using a resistor coupled between the first node and a p-MOS transistor and a substantially constant current source coupled between the p-MOS transistor and the second node.
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18. A transient detection circuit comprising:
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a filter circuit coupled to a first node and a second node, the filter circuit having an output; and an inverter circuit having an input coupled to the output of the filter circuit, the inverter circuit having a voltage switch point that includes an at least substantially constant voltage offset from the first node, wherein the at least substantially constant voltage offset is generated using a substantially constant current source coupled between the first node and a n-MOS transistor and a resistor coupled between the n-MOS transistor and the second node and wherein the inverter circuit has an output, wherein the output is dependent upon a voltage signal at the first node with respect to the second node having a slew rate greater than a predetermined slew rate. - View Dependent Claims (19)
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20. A circuit for providing electrostatic discharge (ESD) protection during an ESD event for internal components in an integrated circuit, the circuit comprising:
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a filter circuit coupled to a first node and to a second node, the filter circuit having an output; an inverter circuit, having an input coupled to the output of the filter circuit, the inverter circuit having a voltage switch point that includes an at least substantially constant voltage offset from the first node, the inverter circuit having an output that is indicative of a detected ESD event, wherein the inverter circuit further includes a current source and a resistor, wherein the at least substantially constant voltage offset includes a voltage drop across the resistor as set by the current source; and an on-time control circuit coupled to the output of the inverter circuit, the on-time control circuit having an output to provide a signal for making conductive at least one clamp switch to provide a discharge path for current from an ESD event. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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Specification