Columnar 1T-N memory cell structure

• US 7,209,378 B2
• Filed: 08/25/2004
• Issued: 04/24/2007
• Est. Priority Date: 08/08/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nejad, Hasan, Seyyedy, Mirmajid
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US10/925,243
• Publication Number:
  US 20050162883A1
• Time in Patent Office: 972 Days
• Field of Search: 365/63, 365/46, 365/51, 365/72, 365/100, 365/148, 365/189.08
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices

Abstract

A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

Claims

1. A memory device comprising:

a plurality of planar memory arrays, each planar memory array comprising a plurality of resistive memory cells arranged in rows and columns, the memory cells of a column being commonly coupled to a sense line, each sense line of an array being commonly electrically coupled to an associated sense line of each of said other memory arrays; and

an access transistor for electrically connecting said commonly electrically coupled sense lines to a sense amplifier during a read operation.

2. The memory device of claim 1, wherein each of said memory cells is a programmable conductor random access memory cell.

3. The memory device of claim 2, wherein each of said programmable conductor random access memory cells comprises a layer of Ge_xSe₁₀₀₋

x, a layer of silver, and a layer of silver selenide.

4. The memory device of claim 3, where x is about 40.

5. The memory device of claim 1, wherein each of said memory cells is a ferroelectric memory cell.

6. The memory device of claim 1, wherein each of said memory cells is a polymer-based memory cell.

7. The memory device of claim 1, wherein each of said memory cells is a phase-changing chalcogenide-based memory cell.

8. The memory device of claim 2, wherein said plurality of planar memory arrays are arranged in a vertical stack.

9. The memory device of claim 2, wherein each said memory cell has an associated sense line and read line, wherein said associated read line and said sense line are orthogonal to each other.

10. The memory device of claim 9, wherein each said read line is used to select an associated memory cell for a read operation.

11. The memory device of claim 10, wherein each said read line is also used to write to an associated memory cell.

12. The memory device of claim 9, further comprising a control line connected to a gate of said access transistor for enabling said access transistor during a read operation of a memory cell coupled to one of said sense lines.

13. The memory device of claim 9, further comprising a row decoder for activating a read line of a selected memory cell, a column decoder for selecting said access transistor, and a planar memory array decoder for selecting a memory array.

14. The memory device of claim 9, wherein all of the memory cells in a column of each said planar array are commonly coupled to said access transistor.

15. A memory device comprising:

a stack of memory cell planes, each of said memory cell planes comprising;

a plurality of memory cells arranged in rows and columns, each of said plurality of memory cells arranged in a column being coupled to an associated column sense line;

an interconnect line for interconnecting one column sense line of each of said stacked planes; and

an access transistor for coupling said interconnect line to a sensing circuit.

16. The memory device of claim 15, wherein each of said memory cells is a programmable conductor random access memory cell.

17. The memory device of claim 15, wherein each of said memory cells is a ferroelectric random access memory cell.

18. The memory device of claim 15, wherein each of said memory cells is a polymer memory cell.

19. The memory device of claim 15, wherein each of said memory cells is a phase-changing chalcogenide memory cell.

20. The memory device of claim 16, wherein said interconnect line interconnects the same column sense line in each of said stacked planes together.

21. The memory device of claim 20, wherein said interconnect is substantially vertical and runs through each of said stacked memory cell planes.

22. The memory device of claim 16, wherein said sensing circuit comprises a sense amplifier having a first input coupled to said access transistor and a second input coupled to receive a reference signal.

23. The memory device of claim 16 further comprising:

a plurality of interconnect lines each for interconnecting an associated one of the column sense lines of each of said stacked memory cell planes; and

a plurality of access transistors each coupling a respective interconnect line to a sensing circuit.

24. The memory device of claim 16 further comprising:

a plurality of interconnect lines each for interconnecting an associated one of the column sense lines of each of said stacked memory cell planes; and

a plurality of access transistors each coupling a respective interconnect line to a respective sensing circuit.

25. The memory device of claim 24, wherein the associated one of the column sense lines from each of said stacked memory cell planes are arranged in a vertical column sense line stack.

26. A memory device comprising:

a plurality of memory slices, each memory slice comprising a plurality of memory cells arranged vertically and horizontally in a plane and which are commonly electrically coupled to a respective sense line interconnect; and

a plurality of access transistors, each electrically coupled to a respective sense line interconnect of a memory slice, each access transistor operating during a read operation to couple a selected memory cell in a slice to a sense amplifier.

27. The memory device of claim 26, wherein each of said memory cells is a programmable conductor random access memory cell.

28. The memory device of claim 26, wherein each of said memory cells is a ferroelectric random access memory cell.

29. The memory device of claim 26, wherein each of said memory cells is a polymer memory cell.

30. The memory device of claim 26, wherein each of said memory cells is a phase-changing chalcogenide memory cell.

31. The memory device of claim 26, wherein each memory cell has an associated read line.

32. The memory device of claim 31, wherein during a read operation said read line is selected by a row decoder, said access transistor is selected by a column decoder.

33. A memory device comprising:

a plurality of access transistors each adapted to be electrically coupled with a sense amplifier;

a plurality of memory slices, each memory slice comprising a stacked

plurality of columns of commonly electrically coupled memory cells, each column of commonly electrically coupled memory cells being electrically coupled to a respective sense line wherein each of said memory cells is a programmable conductor random access memory cell; and

a plurality of sense line interconnects, each said sense line interconnect being electrically coupled between a respective access transistor and the sense lines of a respective memory slice.

34. The memory device of claim 33, further comprising:

a plurality of sensing circuits, each said sensing circuit coupling to said respective access transistor.

35. The memory device of claim 33, further comprising a plurality of read lines respectfully associated with said memory cells for selecting an associated memory cell for a read operation.

36. A computer system comprising:

a central processing unit; and

a memory device electrically coupled to said central processing unit, said memory device comprising;

a plurality of planar memory arrays, each planar memory array comprising a plurality of memory cells arranged in rows and column, each of said memory cells is a programmable conductor random access memory cell, the memory cells of a column being commonly coupled to a sense line, each sense line of an array being commonly electrically coupled to an associated sense line of each of said other memory arrays; and

an access transistor for electrically connecting said commonly electrically coupled sense lines to a sense amplifier during a read operation.

37. The computer system of claim 36, wherein said plurality of planar memory arrays are arranged in a vertical stack.

38. The computer system of claim 36, wherein each said memory cell has an associated sense line and read line, wherein said associated read line and said sense line are orthogonal to each other.

39. The computer system of claim 38, wherein each said read line is used to select an associated memory cell for a read operation.

40. The computer system of claim 39, wherein each said read line is also used to write to an associated memory cell.

41. The computer system of claim 38, further comprising a control line connected to a gate of said access transistor for enabling said access transistor during a read operation of a memory cell coupled to one of said sense lines.

42. The computer system of claim 38, further comprising a row decoder for activating a read line of a selected memory cell, a column decoder for selecting said access transistor, and a planar memory array decoder for selecting a memory array.

43. The computer system of claim 38, wherein all of the memory cells in a column of each said planar array are commonly coupled to said access transistor.

44. A computer system comprising:

a central processing unit; and

a memory device electrically coupled to said central processing unit, said memory device comprising a stack of memory cell planes, each memory cell plane comprising;

a plurality of memory cells arranged in rows and columns, each of said plurality of memory cells arranged in a column being coupled to an associated column sense line, wherein each of said memory cells is a programmable conductor random access memory cell,

an interconnect line for interconnecting one column sense line of each of said stacked planes, and

an access transistor for coupling said interconnect line to a sensing circuit.

45. The computer system as in claim 44, wherein said interconnect line interconnects the same column sense line in each of said stacked planes together.

46. The computer system as in claim 45, wherein said interconnect is substantially vertical and runs through each of said stacked memory cell planes.

47. The computer system as in claim 44, wherein said sensing circuit comprises a sense amplifier having a first input coupled to said access transistor and a second input coupled to receive a reference signal.

48. The computer system as in claim 44 further comprising:

a plurality of interconnect lines each for interconnecting an associated one of the column sense lines of each of said stacked memory cell planes; and

a plurality of access transistors each coupling a respective interconnect line to a sensing circuit.

49. The computer system as in claim 44 further comprising;

a plurality of interconnect lines each for interconnecting an associated one of the column sense lines of each of said stacked memory cell planes; and

a plurality of access transistors each coupling a respective interconnect line to a respective sensing circuit.

50. The computer system as in claim 48, wherein the associated one of the column sense lines from each of said stacked memory cell planes are arranged in a vertical column sense line stack.

51. A computer system comprising:

a central processing unit; and

a memory device electrically coupled to said central processing unit, said memory device comprising;

a plurality of memory slices, each memory slice comprising a plurality of memory cells arranged vertically and horizontally in a plane and which are commonly electrically coupled to a respective sense line interconnect, wherein each of said memory cells is a programmable conductor random access memory cell; and

a plurality of access transistors, each electrically coupled to a respective sense line interconnect of a memory slice, each access transistor operating during a read operation to couple a selected memory cell in a slice to a sense amplifier.

52. The computer system of claim 51, wherein each memory cell has an associated read line.

53. The computer system of claim 52, wherein during a read operation said read line is selected by a row decoder, said access transistor is selected by a column decoder.

54. A computer system comprising:

a central processing unit; and

a memory device electrically coupled to said central processing unit, said computer system comprising;

a plurality of access transistors each adapted to be electrically coupled with a sense amplifier;

a plurality of memory slices, each memory slice comprising a stacked plurality of columns of commonly electrically coupled memory cells, each column of commonly electrically coupled memory cells being electrically coupled to a respective sense line; and

a plurality of sense line interconnects, each said sense line interconnect being electrically coupled between a respective access transistor and the sense lines of a respective memory slice.

55. The computer system of claim 54, further comprising:

a plurality of sensing circuits, each said sensing circuit coupling to said respective access transistor.

56. The computer system of claim 55, further comprising a plurality of read lines respectfully associated with said memory cells for selecting an associated memory cell for a read operation.

57. The computer system of claim 54, wherein each of said memory cells is a phase changing chalcogenide memory cell.

58. The computer system of claim 54, wherein each of said memory cells is a polymer memory cell.

59. The computer system of claim 54, wherein each of said memory cells is a programmable conductor random access memory cell.

60. The computer system of claim 54, wherein each of said memory cells is a ferroelectric random access memory cell.