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Columnar 1T-N memory cell structure

  • US 7,209,378 B2
  • Filed: 08/25/2004
  • Issued: 04/24/2007
  • Est. Priority Date: 08/08/2002
  • Status: Expired due to Term
First Claim
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1. A memory device comprising:

  • a plurality of planar memory arrays, each planar memory array comprising a plurality of resistive memory cells arranged in rows and columns, the memory cells of a column being commonly coupled to a sense line, each sense line of an array being commonly electrically coupled to an associated sense line of each of said other memory arrays; and

    an access transistor for electrically connecting said commonly electrically coupled sense lines to a sense amplifier during a read operation.

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